FPGA的物理不可克隆函數(shù)關(guān)鍵技術(shù)研究
發(fā)布時(shí)間：2018-08-17 20:05
【摘要】：近年來,以智能硬件為主的多樣化終端和交互設(shè)備大規(guī)模普及,使得整個(gè)信息系統(tǒng)更加智能和便捷,其使用環(huán)境的多樣性和復(fù)雜性導(dǎo)致整個(gè)信息系統(tǒng)的風(fēng)險(xiǎn)抵御能力變得十分脆弱。作為一種重要的硬件安全原語,物理不可克隆函數(shù)(PUF)利用不可控的制造工藝隨機(jī)差異生成具有唯一標(biāo)識(shí)的簽名數(shù)據(jù)。自身特有的輕量級(jí)和防篡改屬性在知識(shí)產(chǎn)權(quán)保護(hù)、物聯(lián)網(wǎng)系統(tǒng)安全和硬件設(shè)備認(rèn)證等方面具有廣泛的應(yīng)用前景�；诂F(xiàn)場(chǎng)可編程門陣列(FPGA)的應(yīng)用因其對(duì)電路設(shè)計(jì)可自由靈活配置的特點(diǎn),自身的安全性和可靠性問題越來越受到關(guān)注。PUF技術(shù)可以從硬件層面為FPGA電路提供有效安全保護(hù),以較少的開銷獲得更強(qiáng)的抵御安全風(fēng)險(xiǎn)能力。本文從FPGA PUF的實(shí)現(xiàn)原理、主要特性和應(yīng)用領(lǐng)域等方面入手,系統(tǒng)地分析和論述基于存儲(chǔ)和基于時(shí)延兩大類FPGA PUF的模型和相應(yīng)的電路結(jié)構(gòu),指出現(xiàn)有FPGA PUF設(shè)計(jì)存在片面追求響應(yīng)比特的隨機(jī)性而忽略了電路整體開銷和靈活性的問題。特別深入研究了FPGA PUF設(shè)計(jì)中的三個(gè)關(guān)鍵技術(shù):制造工藝隨機(jī)特性體現(xiàn),可重構(gòu)PUF電路技術(shù)和多節(jié)點(diǎn)密鑰匹配,以提高硬件資源使用效率、增強(qiáng)電路結(jié)構(gòu)靈活性和穩(wěn)定性為主要目標(biāo)開展工作,主要成果包括:(1)以提高硬件資源使用率和兼容性為目標(biāo),設(shè)計(jì)并實(shí)現(xiàn)了一種高資源利用率毛刺PUF電路設(shè)計(jì)方法。針對(duì)毛刺PUF電路設(shè)計(jì)中由于硬件開銷大和兼容性差導(dǎo)致響應(yīng)輸出無法充分體現(xiàn)制造工藝隨機(jī)特性的問題,對(duì)現(xiàn)有毛刺PUF設(shè)計(jì)存在的單一使用狀態(tài)轉(zhuǎn)換時(shí)延差等問題展開研究,根據(jù)可編程邏輯塊(CLB)的不同特性設(shè)置相應(yīng)的布局布線策略,通過改變頂層與底層雙路選擇器的輸入狀態(tài)和調(diào)整開關(guān)矩陣中路徑分配的策略控制到達(dá)兩個(gè)雙路選擇器的時(shí)延差,減少并入雙路選擇器的個(gè)數(shù)的同時(shí)調(diào)整Slice之間相對(duì)位置,確保產(chǎn)生的“毛刺”信號(hào)具有PUF特性。實(shí)驗(yàn)結(jié)果表明,該方法將單位CLB輸出響應(yīng)最高可提升至2比特,并實(shí)現(xiàn)芯片Slice資源100%利用率。(2)針對(duì)可重構(gòu)PUF電路設(shè)計(jì)中存在的靈活程度差,響應(yīng)穩(wěn)定性不高的問題,提出一種交叉可重構(gòu)RO PUF電路設(shè)計(jì)方法。引入交叉可重構(gòu)概念,通過在每一階反相器之間并入級(jí)間交叉結(jié)構(gòu)進(jìn)一步擴(kuò)大RO鏈路組合方式。采用基于LUT的級(jí)間交叉實(shí)現(xiàn)設(shè)計(jì)不僅可以實(shí)現(xiàn)動(dòng)態(tài)配置路徑的目標(biāo),還可以充分利用LUT資源物理位置固定的優(yōu)勢(shì),解決信號(hào)在不同配置電路中傳輸時(shí)延差異過大影響輸出信號(hào)隨機(jī)性的問題。實(shí)驗(yàn)結(jié)果表明,與文獻(xiàn)中其他優(yōu)化結(jié)構(gòu)設(shè)計(jì)相比,該電路結(jié)構(gòu)在可重構(gòu)數(shù)、唯一性和穩(wěn)定性方面都有明顯提升。(3)將FPGA PUF設(shè)計(jì)與實(shí)際應(yīng)用相結(jié)合,針對(duì)目前物聯(lián)網(wǎng)節(jié)點(diǎn)認(rèn)證加密算法在硬件資源消耗和多點(diǎn)認(rèn)證方面存在薄弱環(huán)節(jié)問題,借助本文提出的高資源利用率毛刺PUF電路和交叉可重構(gòu)RO PUF電路設(shè)計(jì),提出了一種基于FPGA PUF的共享密鑰認(rèn)證加密算法。對(duì)基于PUF電路的一對(duì)多認(rèn)證模式相關(guān)設(shè)計(jì)進(jìn)行深入研究。采用交叉可重構(gòu)RO PUF電路為硬件平臺(tái),利用選擇信號(hào)預(yù)先設(shè)置PUF電路,激勵(lì)信號(hào)選取RO對(duì)的方式,調(diào)整兩個(gè)不同的交叉可重構(gòu)RO PUF配置,使其輸出相同的響應(yīng)比特,完成密鑰配對(duì)過程。在此基礎(chǔ)上設(shè)計(jì)了基于共享密鑰的認(rèn)證和數(shù)據(jù)通信協(xié)議基本框架結(jié)構(gòu),并在時(shí)效性和能耗方面進(jìn)一步拓展。實(shí)驗(yàn)表明,相較典型的認(rèn)證加密算法,本文提出的認(rèn)證加密技術(shù)與在保證可靠性的前提下FPGA硬件資源消耗較少,采用一對(duì)多認(rèn)證模式時(shí)該優(yōu)勢(shì)更加明顯。
[Abstract]:In recent years, the large-scale popularization of intelligent hardware-based terminals and interactive devices has made the whole information system more intelligent and convenient. The diversity and complexity of its use environment make the risk resistance ability of the whole information system very fragile. The unique lightweight and tamper-proof attributes of the signature data are widely used in the fields of intellectual property protection, Internet of Things system security and hardware equipment authentication. The application based on field programmable gate array (FPGA) is self-sufficient for circuit design. Due to the characteristics of flexible configuration, more and more attention has been paid to the security and reliability of itself. PUF technology can provide effective security protection for FPGA circuits from the hardware level, and gain a stronger ability to resist security risks with less cost. This paper analyzes and discusses the models and corresponding circuit structures of two types of FPGA PUF: memory-based and delay-based. It points out that the existing design of FPGA PUF has the problem of unilaterally pursuing the randomness of response bits while ignoring the overall cost and flexibility of the circuit. At present, reconfigurable PUF circuit technology and multi-node key matching are the main objectives to improve the efficiency of hardware resource utilization, enhance the flexibility and stability of circuit structure. The main achievements include: (1) To improve the hardware resource utilization and compatibility, a burr-proof PUF circuit design method with high resource utilization is designed and implemented. Aiming at the problem that the response output can not fully reflect the stochastic characteristics of manufacturing process due to the high hardware overhead and poor compatibility in burr PUF circuit design, the problem of single state transition delay in burr PUF design is studied, and the corresponding layout and routing strategy is set according to the different characteristics of programmable logic block (CLB). Simply, by changing the input state of the top-level and bottom-level double-channel selectors and adjusting the strategy of path allocation in the switching matrix, the delay difference between the two double-channel selectors is controlled, the number of parallel double-channel selectors is reduced, and the relative position between the Slices is adjusted to ensure that the "burr" signal has PUF characteristics. Methods The maximum output response per CLB can be upgraded to 2 bits and 100% utilization of chip Slice resources can be realized. (2) To solve the problems of poor flexibility and low response stability in the design of reconfigurable PUF circuits, a cross-reconfigurable RO PUF circuit design method is proposed. The inter-level crossover structure based on LUT can not only achieve the goal of dynamic configuration path, but also make full use of the advantage of fixed physical location of LUT resources to solve the problem of signal transmission delay difference in different configuration circuits affecting the randomness of output signal. The experimental results show that the reconfigurable number, uniqueness and stability of the circuit structure are significantly improved compared with other optimized structure designs in the literature. (3) Combining the design of FPGA PUF with the practical application, there are some weaknesses in the hardware resource consumption and multi-point authentication of node authentication and encryption algorithms in the Internet of Things. In this paper, a shared key authentication and encryption algorithm based on FPGA PUF is proposed with the help of burr PUF circuit with high resource utilization and cross reconfigurable RO PUF circuit design proposed in this paper. Preset the PUF circuit, select the RO pairing mode of the excitation signal, adjust two different cross-reconfigurable RO PUF configurations to output the same response bit and complete the key pairing process. On this basis, the basic framework of authentication and data communication protocol based on shared key is designed, and the timeliness and energy consumption are further expanded. Experiments show that, compared with the typical authentication encryption algorithm, the authentication encryption technology proposed in this paper consumes less hardware resources on the premise of ensuring the reliability of the FPGA, and this advantage is more obvious when one-to-many authentication mode is adopted.
【學(xué)位授予單位】：中國(guó)礦業(yè)大學(xué)(北京)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN791
本文編號(hào)：2188750
[Abstract]:In recent years, the large-scale popularization of intelligent hardware-based terminals and interactive devices has made the whole information system more intelligent and convenient. The diversity and complexity of its use environment make the risk resistance ability of the whole information system very fragile. The unique lightweight and tamper-proof attributes of the signature data are widely used in the fields of intellectual property protection, Internet of Things system security and hardware equipment authentication. The application based on field programmable gate array (FPGA) is self-sufficient for circuit design. Due to the characteristics of flexible configuration, more and more attention has been paid to the security and reliability of itself. PUF technology can provide effective security protection for FPGA circuits from the hardware level, and gain a stronger ability to resist security risks with less cost. This paper analyzes and discusses the models and corresponding circuit structures of two types of FPGA PUF: memory-based and delay-based. It points out that the existing design of FPGA PUF has the problem of unilaterally pursuing the randomness of response bits while ignoring the overall cost and flexibility of the circuit. At present, reconfigurable PUF circuit technology and multi-node key matching are the main objectives to improve the efficiency of hardware resource utilization, enhance the flexibility and stability of circuit structure. The main achievements include: (1) To improve the hardware resource utilization and compatibility, a burr-proof PUF circuit design method with high resource utilization is designed and implemented. Aiming at the problem that the response output can not fully reflect the stochastic characteristics of manufacturing process due to the high hardware overhead and poor compatibility in burr PUF circuit design, the problem of single state transition delay in burr PUF design is studied, and the corresponding layout and routing strategy is set according to the different characteristics of programmable logic block (CLB). Simply, by changing the input state of the top-level and bottom-level double-channel selectors and adjusting the strategy of path allocation in the switching matrix, the delay difference between the two double-channel selectors is controlled, the number of parallel double-channel selectors is reduced, and the relative position between the Slices is adjusted to ensure that the "burr" signal has PUF characteristics. Methods The maximum output response per CLB can be upgraded to 2 bits and 100% utilization of chip Slice resources can be realized. (2) To solve the problems of poor flexibility and low response stability in the design of reconfigurable PUF circuits, a cross-reconfigurable RO PUF circuit design method is proposed. The inter-level crossover structure based on LUT can not only achieve the goal of dynamic configuration path, but also make full use of the advantage of fixed physical location of LUT resources to solve the problem of signal transmission delay difference in different configuration circuits affecting the randomness of output signal. The experimental results show that the reconfigurable number, uniqueness and stability of the circuit structure are significantly improved compared with other optimized structure designs in the literature. (3) Combining the design of FPGA PUF with the practical application, there are some weaknesses in the hardware resource consumption and multi-point authentication of node authentication and encryption algorithms in the Internet of Things. In this paper, a shared key authentication and encryption algorithm based on FPGA PUF is proposed with the help of burr PUF circuit with high resource utilization and cross reconfigurable RO PUF circuit design proposed in this paper. Preset the PUF circuit, select the RO pairing mode of the excitation signal, adjust two different cross-reconfigurable RO PUF configurations to output the same response bit and complete the key pairing process. On this basis, the basic framework of authentication and data communication protocol based on shared key is designed, and the timeliness and energy consumption are further expanded. Experiments show that, compared with the typical authentication encryption algorithm, the authentication encryption technology proposed in this paper consumes less hardware resources on the premise of ensuring the reliability of the FPGA, and this advantage is more obvious when one-to-many authentication mode is adopted.
【學(xué)位授予單位】：中國(guó)礦業(yè)大學(xué)(北京)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN791
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相關(guān)期刊論文 前2條
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