【摘要】：系統(tǒng)芯片間對數(shù)據(jù)傳輸速率的要求不斷提高,使得串行器／解串器(Serializer and Deserializer, SerDes)技術(shù)得到了越來越多的關(guān)注。由于測試設(shè)備帶寬需大于信號速率,且探針接入會對信號產(chǎn)生影響,因而對高速SerDes (HSS)功能芯片知識產(chǎn)權(quán)(IP)進(jìn)行誤碼率與眼圖的測試成為挑戰(zhàn)。 為了對高速信號眼圖測試,本論文設(shè)計了片上眼開監(jiān)視器電路。相比于傳統(tǒng)的基于模板的二維眼開監(jiān)視器電路,本論文提出的設(shè)計方案無需進(jìn)行初始采樣時鐘與眼圖中心對齊的操作,測試過程設(shè)置與測試結(jié)果記錄由數(shù)字控制模塊完成。所提出的片上眼開監(jiān)視器方案具有獲得一個周期內(nèi)信號眼圖打開大小信息的特點。在TSMC65nm工藝下,片上眼開監(jiān)視器可完成對單鏈路12.5Gbps信號眼圖的測試,垂直偏差20mV,水平偏差4ps。 為了實現(xiàn)對HSS電路的誤碼率測試,本論文設(shè)計了片上偽隨機(jī)碼的產(chǎn)生檢測電路與測試路徑。為了實現(xiàn)對核內(nèi)寄存器的讀寫,本論文設(shè)計了基于串口與JTAG協(xié)議的接口訪問電路。在TSMC65nm工藝下,8位并行產(chǎn)生模塊運行頻率為3.2GHz,8位檢測模塊運行頻率為1.8GHz,可應(yīng)用于12.5Gbps的HSS電路中進(jìn)行誤碼率的測試。 為了實現(xiàn)對仿真系統(tǒng)中誤碼率的測試,本論文提出了基于噪聲模型和統(tǒng)計理論的系統(tǒng)誤碼率評價方法。通過矩估計量與樣本容量的選取,可對仿真系統(tǒng)的誤碼率進(jìn)行快速評價�；谖覀兲岢龅慕y(tǒng)計測試信噪比的方法,當(dāng)樣本容量選為3100,此時樣本方差估計總體方差的誤差在5%內(nèi)的置信度達(dá)到95%,對于10-12誤碼率估計偏差小于一個數(shù)量級。 本論文對眼圖與誤碼率測試HSS電路的性能是定性與定量兩個方面的評價,提出電路系統(tǒng)與仿真系統(tǒng)中使用眼開監(jiān)視器、內(nèi)建自測試與噪聲分析的測試方案,實現(xiàn)了對HSS功能芯片IP核的眼圖與誤碼率的仿真測試。
[Abstract]:The requirement of data transmission rate between chips is increasing, which makes the serial / demultiplexer (Serializer and Deserializer, SerDes) technology get more and more attention. Because the bandwidth of the test equipment needs to be larger than the signal rate and the probe access will affect the signal, it is a challenge to test the bit error rate (BER) and the eye diagram of the intellectual property (IP) of the high-speed SerDes (HSS) functional chip. In order to test the high-speed signal eye chart, this paper designs the on-chip eye-open monitor circuit. Compared with the traditional two dimensional open eye monitor circuit based on template, the design of this paper does not need the operation of initial sampling clock and eye image center alignment, and the test process setting and test result recording are completed by digital control module. The proposed on-chip eye monitor scheme has the characteristics of obtaining the information of the opening size of the eye chart of the signal within a period. In the TSMC65nm process, the on-chip eye monitor can complete the test of the single link 12.5Gbps signal eye diagram, the vertical deviation is 20mV, and the horizontal deviation is 4ps. In order to test the bit error rate (BER) of HSS circuit, this paper designs the generation and detection circuit and test path of pseudorandom code on chip. In order to read and write registers in the core, the interface access circuit based on serial port and JTAG protocol is designed in this paper. The operating frequency of the 8-bit parallel generation module in TSMC65nm is 1.8 GHz, which can be used in the HSS circuit of 12.5Gbps to test the bit error rate (BER). In order to test the bit error rate (BER) in the simulation system, this paper presents a method of BER evaluation based on noise model and statistical theory. Through the selection of moment estimator and sample size, the bit error rate of the simulation system can be evaluated quickly. Based on the SNR method proposed by us, when the sample size is chosen as 3100, the confidence of the total variance of sample estimation is 95%, and the error of 10-12 BER estimation is less than one order of magnitude. In this paper, the performance of eye map and bit error rate (BER) HSS circuits is evaluated qualitatively and quantitatively. A test scheme of using eye monitor, built-in self-test and noise analysis in circuit system and simulation system is proposed. The eye diagram and bit error rate of HSS function chip IP core are simulated and tested.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN407

【參考文獻(xiàn)】

相關(guān)期刊論文 前4條

1 張俊杰;徐震柳;田進(jìn)進(jìn);鄭s，

本文編號：2157816