本文選題：高壓功率器件 + 絕緣柵雙極晶體管��； 參考：《浙江大學(xué)》2013年博士論文

【摘要】：IGBT作為最新一代的復(fù)合全控型功率器件,具有電壓控制、輸入阻抗大、驅(qū)動(dòng)功率小、控制電路簡(jiǎn)單、開(kāi)關(guān)損耗小、工作頻率高等諸多優(yōu)點(diǎn),而高壓IGBT在電機(jī)控制、新能源、軌道交通、智能電網(wǎng)、電動(dòng)汽車等領(lǐng)域起著不可替代的作用。由于國(guó)內(nèi)工藝技術(shù)水平相對(duì)落后,高壓IGBT的設(shè)計(jì)與生產(chǎn)長(zhǎng)期落后于國(guó)外。本課題旨在結(jié)合現(xiàn)有國(guó)內(nèi)工藝,研發(fā)具有自主知識(shí)產(chǎn)權(quán)的高壓IGBT芯片,為高壓IGBT在國(guó)內(nèi)的研發(fā)和實(shí)現(xiàn)積累一定的經(jīng)驗(yàn)。 功率器件可靠性問(wèn)題已經(jīng)成為影響功率模塊整體性能的關(guān)鍵問(wèn)題之一。本論文通過(guò)對(duì)功率器件SG-NLDMOS在熱流子退化及關(guān)態(tài)雪崩擊穿下的退化進(jìn)行仿真與實(shí)驗(yàn)研究,揭示其退化機(jī)制,并提出改進(jìn)措施。此項(xiàng)研究可為功率器件的可靠性設(shè)計(jì)及評(píng)估體系提供一定的參考價(jià)值。 本論文的主要工作及創(chuàng)新點(diǎn)包括： 1、提出高壓IGBT的設(shè)計(jì)方法,設(shè)計(jì)并實(shí)現(xiàn)了一款1700V/100A高壓大電流NPT-IGBT,包括其元胞結(jié)構(gòu)、終端結(jié)構(gòu)、工藝流程及版圖的設(shè)計(jì)。通過(guò)分析及仿真確定元胞的結(jié)構(gòu)參數(shù)；采用場(chǎng)限環(huán)與場(chǎng)板相結(jié)合的終端結(jié)構(gòu),討論場(chǎng)板的設(shè)置對(duì)終端結(jié)構(gòu)的影響,提出多晶硅場(chǎng)板設(shè)置的方案；對(duì)IGBT背面的集電極工藝進(jìn)行探索及優(yōu)化；簡(jiǎn)化工藝流程,應(yīng)用六塊光刻版完成整個(gè)工藝流程；設(shè)計(jì)了柵電極置中的版圖結(jié)構(gòu)。 2、提出了雙面N+擴(kuò)散殘留層的新結(jié)構(gòu)來(lái)改善平面柵型IGBT的JFET電阻,在改善器件導(dǎo)通壓降的同時(shí),擊穿電壓沒(méi)有發(fā)生顯著的下降；把N+擴(kuò)散殘留層應(yīng)用到溝槽柵型IGBT當(dāng)中,提出了DR-IGBT的結(jié)構(gòu),并與傳統(tǒng)的NPT-IGBT和LPT CSTBT進(jìn)行比較。與傳統(tǒng)的NPT-IGBT相比,在相同的擊穿電壓下,其導(dǎo)通壓降與電流能力更優(yōu)；與LPT CSTBT相比,擊穿電壓更高,而導(dǎo)通壓降則在大電流密度下比LPT CSTBT更低；引入背面P-緩沖層,提出了NPN管輔助快速開(kāi)關(guān)的IGBT(NFS-IGBT)新結(jié)構(gòu),具有更好的導(dǎo)通壓降與關(guān)斷時(shí)間的折衷。 3、采用中子嬗變摻雜的區(qū)熔單晶硅作為襯底,制作了多目標(biāo)光刻版,流片完成后進(jìn)行半橋模塊的封裝,并對(duì)IGBT器件進(jìn)行了測(cè)試。擊穿電壓達(dá)到1700V以上,125℃下工作電流100A；閾值電壓5.2V左右、柵發(fā)射極漏電流小于80nA、關(guān)斷時(shí)間0.744μs、關(guān)斷功耗25mJ,都達(dá)到設(shè)計(jì)要求,只是導(dǎo)通壓降略高(3.7V)。 4、采用直流電壓應(yīng)力實(shí)驗(yàn)TCAD仿真、電荷泵測(cè)試,對(duì)SG-NLDMOS器件的熱載流子效應(yīng)進(jìn)行研究,揭示熱載流子效應(yīng)與柵壓相關(guān),在中等柵壓下,熱載流子退化發(fā)生在積累區(qū),界面態(tài)和氧化層陷阱電荷同時(shí)發(fā)生作用；在高柵壓下,退化發(fā)生在側(cè)墻區(qū),界面態(tài)起主導(dǎo)作用；研究了結(jié)構(gòu)參數(shù)Ndd對(duì)熱載流子效應(yīng)的影響,并提出了改善措施。采用電流脈沖應(yīng)力實(shí)驗(yàn)、TCAD仿真和電荷泵測(cè)試,研究了SG-NLDMOS的關(guān)態(tài)雪崩擊穿退化機(jī)制,發(fā)現(xiàn)雪崩擊穿退化近似于高柵壓和中等柵壓下熱載流子退化的疊加,氧化層陷阱正電荷主要產(chǎn)生于積累區(qū),而界面態(tài)在整個(gè)漂移區(qū)中都有增加。
[Abstract]:As the latest generation of the composite full control power device, IGBT has the advantages of voltage control, large input impedance, small driving power, simple control circuit, small switching loss and high working frequency, and high voltage IGBT plays an irreplaceable role in the field of motor control, new energy, rail traffic, smart grid, electric vehicle and so on. The technical and technical level is relatively backward, the design and production of high voltage IGBT lag behind the foreign countries for a long time. This topic aims to develop high voltage IGBT chips with independent intellectual property in combination with existing domestic technology, and accumulate certain experience for the research and development and Realization of high voltage IGBT in China.
The reliability of power devices has become one of the key problems that affect the overall performance of power modules. Through the simulation and experimental study of the degradation of the power device SG-NLDMOS under the heat flux degradation and the close state avalanche breakdown, the degradation mechanism is revealed and the improvement measures are put forward. This study can be used for the reliability of power devices. It provides a certain reference value for the evaluation system.
The main work and innovation of this paper include:
1, the design method of high voltage IGBT is put forward, and a 1700V/100A high voltage and large current NPT-IGBT is designed and implemented, including its cellular structure, terminal structure, process flow and layout design. The structure parameters of the cell are determined by analysis and simulation, and the terminal structure combining field limit ring and field plate is adopted to discuss the terminal structure of the field plate. The scheme of setting the polysilicon field board is proposed, and the collector process on the back of IGBT is explored and optimized; the process flow is simplified, the whole process flow is completed with six lithography plates, and the layout structure of the grid electrode is designed.
2, a new structure of the double-sided N+ diffusion residual layer is proposed to improve the JFET resistance of the plane gate type IGBT. The breakdown voltage is not significantly reduced while the device's conduction pressure drop is improved; the N+ diffusion residual layer is applied to the groove gate IGBT, and the structure of the DR-IGBT is proposed and compared with the traditional NPT-IGBT and LPT CSTBT. Compared with the NPT-IGBT, the pressure drop and current capacity are better under the same breakdown voltage, and the breakdown voltage is higher than that of LPT CSTBT, while the conduction pressure drop is lower than that of LPT CSTBT at the large current density; the back P- buffer layer is introduced, and a new IGBT (NFS-IGBT) structure with the auxiliary fast switch of the NPN tube is proposed, which has a better conduction pressure drop and a better conduction pressure drop. The tradeoff between closing time.
3, the multi target photolithography plate is made with the neutron transmutation doped monocrystalline silicon as substrate. After the flow sheet is completed, the half bridge module is encapsulated, and the IGBT device is tested. The breakdown voltage is above 1700V, the working current is 100A at 125 C, the threshold voltage is about 5.2V, the gate emitter leakage current is less than 80nA and the closing time is 0.744 U S. The power consumption of 25mJ is up to the design requirement, but the conduction voltage drop is slightly higher (3.7V).
4, a DC voltage stress experiment TCAD simulation, a charge pump test, is used to study the hot carrier effect of the SG-NLDMOS device. It is revealed that the hot carrier effect is related to the gate pressure. Under the middle gate pressure, the thermal carrier degradation occurs in the accumulating area, and the interface state and the oxide trap charge are simultaneously affected, and the degradation occurs at the side wall under the high gate pressure. The influence of the structure parameter Ndd on the hot carrier effect is studied and the improvement measures are proposed. The breakdown mechanism of the close state avalanche in SG-NLDMOS is studied by the current pulse stress experiment, the TCAD simulation and the charge pump test. It is found that the avalanche breakdown and deionization are approximate to the high gate pressure and the middle gate pressure drop back. The superposition of the oxide trap is mainly due to the accumulation of positive charges, while the interface state increases in the drift region.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2013
【分類號(hào)】：TN322.8

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