本文選題：UHF + RFID閱讀器��； 參考：《南京航空航天大學(xué)》2013年碩士論文

【摘要】：隨著集成電路制造工藝的發(fā)展、設(shè)計工具自動化程度與設(shè)計技術(shù)的提高，單個芯片上能夠集成的電路功能也變得越來越復(fù)雜。集成電路由專用集成電路ASIC（Application SpecificIntegrated Circuit）向片上系統(tǒng)SoC（System on Chip）方向發(fā)展的形勢日趨明顯。包含處理器在內(nèi)的系統(tǒng)級芯片集成技術(shù)，可以較好降低系統(tǒng)整體的功耗、面積，提高芯片運(yùn)行速度，提升芯片性能。目前，基于IP（Intellectual Property，知識產(chǎn)權(quán)）核的片上系統(tǒng)設(shè)計，是超大規(guī)模集成電路設(shè)計的核心領(lǐng)域。 RFID（Radio Frequency Identification，射頻識別）閱讀器是射頻識別產(chǎn)品的重要組成部分。相比其他頻段，，超高頻段的RFID具有以下幾個明顯的優(yōu)勢：識別距離較遠(yuǎn)、傳輸速度高、操作快捷、可實現(xiàn)多目標(biāo)識別、移動目標(biāo)識別等。目前，大部分射頻識別設(shè)備尤其是手持式設(shè)備均工作在超高頻段。隨著超高頻RFID設(shè)備的大范圍使用和技術(shù)改進(jìn)，閱讀器的單芯片解決方案已經(jīng)成為行業(yè)發(fā)展趨勢。數(shù)字基帶信號處理是閱讀器芯片設(shè)計的組成部分，將這部分功能采用片上系統(tǒng)的設(shè)計方法實現(xiàn)，是完成單芯片閱讀器的重要基礎(chǔ)。 本課題依據(jù)ISO18000-6C協(xié)議要求，完成RFID閱讀器數(shù)字基帶信號處理的片上系統(tǒng)設(shè)計。應(yīng)用了開源資源網(wǎng)站Opencores.org維護(hù)和提供的OpenRisc OR1200處理器內(nèi)核以及一系列IP核，系統(tǒng)的總線采用OpenRisc所支持的開源片上總線Wishbone，自行設(shè)計完成協(xié)議處理單元IP核，實現(xiàn)功能包括基帶信號PIE編碼、FM0解碼與CRC-5/CRC-16校驗，完成數(shù)據(jù)的發(fā)送與接收，并根據(jù)Wishbone總線協(xié)議配置相應(yīng)的設(shè)備接口，從而實現(xiàn)基帶信號處理IP核設(shè)計。片上RAM、PLL等由Quartus II提供的工具生成。硬件采用自上而下的設(shè)計方法，完成各個IP核的分析設(shè)計和功能仿真，再將各個IP核互聯(lián)實現(xiàn)硬件設(shè)計。搭建系統(tǒng)軟件開發(fā)所需的GNU工具鏈環(huán)境，編碼設(shè)計完成硬件系統(tǒng)的啟動與應(yīng)用程序。最終實現(xiàn)閱讀器的基帶處理SoC系統(tǒng)軟硬件設(shè)計。系統(tǒng)的驗證工作通過Modelsim仿真軟件和FPGA開發(fā)板實現(xiàn)。
[Abstract]:With the development of IC manufacturing technology, the automation of design tools and the improvement of design technology, the integrated circuit functions on a single chip become more and more complex. The development of integrated circuits from ASIC / ASIC Application specific Integrated Circuit (ASIC) to SoCon system on Chip (SOC) is becoming more and more obvious. The integrated technology of system level chip, including processor, can reduce the power consumption and area of the whole system, improve the speed of the chip and improve the performance of the chip. At present, the on-chip system design based on IP IP intellectual property (IP) core is the core field of VLSI design. RFID Radio Frequency Identification (RFID) reader is an important part of RFID products. Compared with other frequency bands, UHF RFID has the following obvious advantages: the identification distance is long, the transmission speed is high, the operation is fast, and the multi-target identification and moving target identification can be realized. At present, most RFID devices, especially hand-held devices, work in UHF. With the wide use and technical improvement of UHF RFID devices, the single-chip solution of readers has become a trend in the industry. Digital baseband signal processing is an integral part of reader chip design. It is an important foundation to complete single-chip reader by adopting the design method of on-chip system. This subject is based on ISO18000-6C protocol. Complete RFID reader digital baseband signal processing system design. OpenRisc OR1200 processor kernel and a series of IP cores, which are maintained and provided by Opencores.org, are applied. The system bus adopts Wishbone, an open source on-chip bus supported by OpenRisc, to design and complete the protocol processing unit IP core. The realization functions include baseband signal PIE-coding FM0 decoding and CRC-5 / CRC-16 check, data sending and receiving, and configuration of corresponding device interface according to Wishbone bus protocol, so as to realize the design of baseband signal processing IP core. On-chip RAM PLL and so on are generated by tools provided by Quartus II. The hardware adopts the top-down design method to complete the analysis design and function simulation of each IP core, and then interconnect each IP core to realize the hardware design. The GNU toolchain environment is built for the software development of the system, and the hardware system startup and application program are designed and coded. Finally, the hardware and software design of the baseband processing SoC system is realized. The verification of the system is realized by Modelsim simulation software and FPGA development board.
【學(xué)位授予單位】：南京航空航天大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP391.44

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