【摘要】：厚膜絕緣體上硅(SOI)工藝具有隔離性能好、抗輻射能力強(qiáng)和寄生參數(shù)小等優(yōu)點(diǎn),而橫向絕緣柵極極型晶體管(LIGBT)器件具有擊穿電壓高、電流能力強(qiáng)及可集成的特點(diǎn),因此厚膜SOI-LIGBT器件受到了功率集成電路的青睞,在智能家電、電動(dòng)汽車、工業(yè)控制和顯示驅(qū)動(dòng)等領(lǐng)域有著廣泛的應(yīng)用,成為未來智能功率集成電路的核心元件之一。然而,厚膜SOI-LIGBT器件實(shí)際工作過程中的外部靜電沖擊、高工作電壓、大電流密度、功耗帶來的自熱效應(yīng)等問題導(dǎo)致器件在實(shí)際工作過程中面臨著嚴(yán)峻的可靠性問題。這些可靠性問題決定了芯片的可靠性等級(jí)和應(yīng)用范圍,限制了智能功率集成電路的進(jìn)一步發(fā)展。因此,本文針對(duì)厚膜SOI-LIGBT器件最為關(guān)鍵的靜電泄放(ESD)沖擊、熱載流子(HCI)損傷和閂鎖效應(yīng)(Latch-up)三個(gè)方面的可靠性問題進(jìn)行了系統(tǒng)的研究。該研究對(duì)厚膜SOI-LIGBT器件和相應(yīng)功率集成電路的可靠性評(píng)估具有實(shí)際參考意義,對(duì)厚膜SOI-LIGBT的可靠性優(yōu)化設(shè)計(jì)提供了理論依據(jù)和指導(dǎo)。本文的主要工作和創(chuàng)新如下：1、研究了厚膜SOI-LIGBT器件在ESD沖擊下柵極耦合階段、電壓回滯階段和電壓維持階段的響應(yīng)特性,揭示了器件在ESD沖擊下的失效機(jī)理�；陧憫�(yīng)特性和失效機(jī)理的研究建立了厚膜SOI-LIGBT器件的ESD響應(yīng)特性的行為模型,模型誤差在10%以內(nèi)。在此基礎(chǔ)上,提出了一種高魯棒性的柵電極分段接地結(jié)構(gòu)SOI-LIGBT器件。該器件在損失一定電流能力(5-10%)的情況下顯著提升了器件的ESD能力(大于20%)。2、揭示了厚膜SOI-LIGBT器件的HCI退化機(jī)理,并指出漂移區(qū)的損傷對(duì)厚膜SOI-LIGBT性能退化幾乎沒有影響。研究發(fā)現(xiàn),器件的最壞HCI應(yīng)力為高柵極電壓應(yīng)力,最壞應(yīng)力下的HCI退化主要由器件溝道區(qū)的界面態(tài)產(chǎn)生和熱電子注入主導(dǎo)。研究了器件開關(guān)轉(zhuǎn)換階段的損傷在整個(gè)應(yīng)力過程中的作用,從而建立了器件在動(dòng)態(tài)應(yīng)力下的HCI退化壽命模型,模型的最大誤差小于7%。3、提出了兩種高HCI可靠性的SOI-LIGBT新結(jié)構(gòu)。其中陽極N+環(huán)結(jié)構(gòu)可以通過折中器件電流能力的方式有效降低器件的HCI退化,而鳥嘴處帶有額外P型區(qū)結(jié)構(gòu)器件可以在不影響器件其它性能的情況下顯著提升器件的HCI可靠性。4、分析了厚膜SOI-LIGBT器件的閂鎖機(jī)理。建立了器件中空穴電流的模型,所建空穴電流模型的均方根誤差小于1%,最大誤差小于3%。進(jìn)而完成了器件的閂鎖電壓模型,該模型考慮了溫度對(duì)器件閂鎖安全工作區(qū)的影響。5、提出了兩種高抗閂鎖能力SOI-LIGBT器件結(jié)構(gòu)。其中陰極帶有深P型埋層結(jié)構(gòu)器件在損失器件一定電流能力(小于10%)的情況下將器件的閂鎖電壓提高了60%,而Trench接地結(jié)構(gòu)在不增加任何工藝步驟且不影響器件其它性能的情況下將器件的閂鎖電壓提高了25%。
[Abstract]:Silicon (SOI) technology on thick film insulators has the advantages of good isolation performance, strong radiation resistance and low parasitic parameters, while transverse insulated gate transistor (LIGBT) devices have the characteristics of high breakdown voltage, strong current ability and integration. Therefore, thick film SOI-LIGBT devices are favored by power integrated circuits and are widely used in intelligent household appliances, electric vehicles, industrial control and display drive. It will become one of the core components of intelligent power integrated circuits in the future. However, the external electrostatic shock, high operating voltage, high current density and self-heating effect caused by power consumption of thick film SOI-LIGBT devices lead to serious reliability problems in the actual working process. These reliability problems determine the reliability level and application range of the chip, and limit the further development of intelligent power integrated circuits. Therefore, the reliability of (ESD) shock, hot carrier (HCI) damage and latch effect (Latch-up), which are the most critical aspects of thick film SOI-LIGBT devices, is systematically studied in this paper. This study has practical reference significance for the reliability evaluation of thick film SOI-LIGBT devices and corresponding power integrated circuits, and provides a theoretical basis and guidance for the reliability optimization design of thick film SOI-LIGBT. The main work and innovations of this paper are as follows: 1. The response characteristics of thick film SOI-LIGBT devices under ESD shock gate coupling stage, voltage lag stage and voltage maintenance stage are studied, and the failure mechanism of the device under ESD shock is revealed. Based on the study of response characteristics and failure mechanism, the behavior model of ESD response characteristics of thick film SOI-LIGBT devices is established, and the model error is less than 10%. On this basis, a highly robust gate segmented grounding structure SOI-LIGBT device is proposed. Under the condition of losing a certain current capacity (5 鈮，

本文編號(hào)：2505307