【摘要】：近年來隨著我國航天科技不斷攀升,對輻照環(huán)境應(yīng)用微處理器的高可靠性需求越發(fā)迫切。SRAM作為微處理器核心存儲部件占用較大芯片面積,并且對輻照引發(fā)的單粒子翻轉(zhuǎn)效應(yīng)(SEU)極為敏感。SEU誘導(dǎo)SRAM產(chǎn)生軟錯誤后,能夠?qū)е挛⑻幚砥鞑荒苷９ぷ?因此開展SRAM的SEU和軟錯誤研究十分必要。工藝尺寸進(jìn)入納米級后,集成電路器件間的電荷共享愈發(fā)嚴(yán)重,使得納米級SRAM單元的SEU敏感性發(fā)生改變,導(dǎo)致已有多種加固方法失效。同時,小尺寸SRAM單元中也產(chǎn)生了新的單粒子翻轉(zhuǎn)恢復(fù)效應(yīng)(SEUR),通過增強(qiáng)SEUR可降低SRAM的SEU敏感性�；谌S堆疊技術(shù)的3D SRAM把傳統(tǒng)SRAM在垂直方向上進(jìn)行堆疊,并使用TSV進(jìn)行垂直互聯(lián),解決了傳統(tǒng)SRAM遇到的諸多瓶頸,但處于輻照環(huán)境中的3D SRAM依然會受到SEU危害而產(chǎn)生軟錯誤。3D SRAM堆疊結(jié)構(gòu)使SEU產(chǎn)生和傳播更加復(fù)雜,進(jìn)而增加了3D SRAM軟錯誤分析的難度。同時,三維堆疊技術(shù)使用的TSV會與入射單粒子發(fā)生碰撞,進(jìn)而對3D SRAM軟錯誤特性產(chǎn)生影響。針對納米級SRAM單元和3D SRAM中SEU和軟錯誤的新特性,本文開展了相關(guān)研究并取得了以下幾個方面的研究成果:(1)利用3D TCAD全器件模擬,研究電荷共享對納米級SRAM單元SEU敏感特性的影響。根據(jù)40nm商用SRAM單元版圖,對單元內(nèi)所有晶體管均建立3D TCAD器件模型。然后分別在有/無電連接關(guān)系和不同LET條件下模擬得到SEU敏感面積。模擬結(jié)果表明電荷共享可使PMOS的SEU敏感面積減小37.5%,使NMOS的SEU敏感面積減小65.1%。通過深入分析不同條件下SEU敏感面積的差別,發(fā)現(xiàn)基于電荷共享的SEUR可以減小PMOS的SEU敏感性,而開態(tài)PMOS通過幫助吸收沉積電荷并產(chǎn)生補(bǔ)償電流來減小NMOS的SEU敏感面積。此外,研究還表明SRAM單元中NMOS比PMOS更加敏感。(2)分別深入研究SRAM單元內(nèi)關(guān)態(tài)PMOS和開態(tài)PMOS之間,以及關(guān)態(tài)PMOS和開態(tài)NMOS之間的SEUR效應(yīng),并討論增強(qiáng)SEUR的方法。基于TCAD器件/電路混合模擬,發(fā)現(xiàn)關(guān)態(tài)PMOS和開態(tài)PMOS間SEUR的產(chǎn)生不僅依賴于電荷共享,并且還需要從級器件的電荷收集強(qiáng)于主級器件的電荷收集。提出了DSD和DPI兩種版圖布局來增強(qiáng)兩PMOS間的SEUR。垂直入射模擬中同傳統(tǒng)版圖相比,DSD和DPI版圖可以分別減少4.26%和31.56%的SEU敏感面積。在斜入射模擬中只有DPI版圖可極大增加SEUR的產(chǎn)生概率。本文還研究了由關(guān)態(tài)PMOS的電荷收集和開態(tài)NMOS的延遲電荷收集觸發(fā)的新型SEUR。此SEUR受PMOS影響較小而受NMOS影響較大,減少同反相器中PMOS和NMOS間距可以增強(qiáng)這種SEUR,并且其誘導(dǎo)SET的寬度飽和值等于SEU產(chǎn)生時間與SRAM單元反饋延遲之和。(3)利用基于蒙特卡洛方法的SRIM和Geant4工具研究3D SRAM堆疊結(jié)構(gòu)對軟錯誤特性的影響。利用SRIM工具分析重離子在三維堆疊結(jié)構(gòu)中的射程,模擬結(jié)果表明重離子能量大于22MeV/u后即可穿過6層管芯堆疊的模型,由此可知3D SRAM中每層都可能會產(chǎn)生軟錯誤。利用Geant4模擬得到復(fù)雜三維堆疊結(jié)構(gòu)模型中各層管芯敏感層中的沉積電荷量,分析發(fā)現(xiàn)在低能重離子轟擊條件下,各層管芯的軟錯誤特性有較大不同,但在高能重離子轟擊條件下,這種差別會消失,并且底層管芯更容易發(fā)生較為嚴(yán)重的MCU。研究中還發(fā)現(xiàn)TSV對入射重離子具有阻礙作用,并且TSV可以降低周圍敏感單元的翻轉(zhuǎn)截面。(4)搭建3D SRAM軟錯誤分析平臺,分析3D SRAM的軟錯誤特性。利用業(yè)界公認(rèn)的SET、SEU模擬方法和成熟工具,建立3D SRAM軟錯誤分析平臺,此平臺可快速、準(zhǔn)確分析和評估3D SRAM的軟錯誤�；诖似脚_對同規(guī)模的2D SRAM、字線劃分3D SRAM和位線劃分3D SRAM分別進(jìn)行了軟錯誤分析。分析結(jié)果表明:垂直轟擊靜態(tài)測試中三種SRAM的翻轉(zhuǎn)截面幾乎相同,但隨機(jī)入射角模擬中3D SRAM翻轉(zhuǎn)截面要大于2D SRAM;靜態(tài)測試中字線劃分3D SRAM會產(chǎn)生更加嚴(yán)重的MBU,因此位線劃分3D SRAM更加適合應(yīng)用于輻照環(huán)境;動態(tài)測試中三種SRAM的組合邏輯電路被轟擊后都會引發(fā)嚴(yán)重的MBU;由于TSV周圍敏感單元數(shù)量較少,TSV只能降低3%左右的翻轉(zhuǎn)截面。
[Abstract]:With the increasing of space science and technology in our country in recent years, the high-reliability demand for application of microprocessor to radiation environment becomes more and more urgent. SRAM, as a core storage component of the microprocessor, occupies a larger chip area and is extremely sensitive to the single particle inversion effect (SEU) initiated by irradiation. It is necessary to carry out SEU and soft error research of SRAM after the SEU induced soft error in SRAM. after the process size enters the nanometer level, the charge sharing between the integrated circuit devices becomes more serious, so that the SEU sensitivity of the nano-scale SRAM cells is changed, and a plurality of reinforcing methods are caused to fail. At the same time, a new single particle inversion recovery effect (SEUR) is also generated in small size SRAM cells, which can reduce the SEU sensitivity of SRAM by enhancing SEUR. The 3D SRAM based on the three-dimensional stacking technology stacks the traditional SRAM in the vertical direction, and the vertical interconnection is performed using the TSVs, so that a plurality of bottlenecks encountered by the conventional SRAM are solved, However, the 3D SRAM in the irradiation environment will still suffer from the SEU hazard. The 3D SRAM stack structure makes SEU generate and propagate more complex, and then increases the difficulty of soft error analysis of 3D SRAM. meanwhile, the TSV used by the three-dimensional stacking technology can collide with the incident single particle, and further influence the soft error characteristics of the 3D SRAM. In view of the new features of SEU and soft error in nanoscale SRAM cells and 3D SRAM, the relevant research has been carried out and the following achievements have been obtained: (1) The effect of charge sharing on the SEU sensitive characteristics of nanoscale SRAM cells is studied by using 3D TCAD system-wide simulation. Based on the 40nm commercial SRAM cell layout, 3D TCAD device model was built for all transistors in the cell. The SEU sensitive area is then simulated under/ without electrical connection and under different LET conditions, respectively. The simulation results show that charge sharing can reduce the SEU sensitive area of PMOS by 37. 5%, and reduce the SEU sensitive area of NMOS by 65.1%. By analyzing the difference of SEU sensitive area under different conditions, it is found that SEUR based on charge sharing can reduce the SEU sensitivity of PMOS, while on-state PMOS reduces the SEU sensitive area of NMOS by helping to absorb the deposited charge and generate compensation current. In addition, the study shows that NMOS is more sensitive to NMOS than PMOS in SRAM cells. (2) the SEUR effect between the off-state PMOS and the ON-state PMOS and the OFF-state PMOS and the ON-state NMOS are researched in the SRAM cell respectively, and the method for enhancing SEUR is also discussed. Based on the TCAD device/ circuit hybrid simulation, it is found that the generation of SEUR between the off-state PMOS and the ON-state PMOS depends not only on charge sharing, but also the charge collection from the stage device is stronger than that of the main-stage device. Two layouts of DSD and DPI are proposed to enhance the SEUR between two PMOS transistors. Compared with the traditional layout in the vertical incident simulation, the DSD and DPI layout can reduce the SEU sensitive area of 4.26% and 31. 56%, respectively. Only DPI layout can greatly increase the generation probability of SEUR in oblique incidence simulation. This paper also studies the new SEUR of delayed charge collection triggered by charge-collection and open-state NMOS of off-state PMOS. This SEUR is affected by the PMOS and is greatly influenced by the NMOS, so that the SEUR can be enhanced by reducing the PMOS and NMOS spacing in the same inverter, and the width saturation value of the induced SET is equal to the sum of the SEU generation time and the SRAM cell feedback delay. (3) Using the SRIM and Geant4 tools based on Monte Carlo method to study the effect of 3D SRAM stack structure on soft error characteristics. Using the SRIM tool to analyze the range of heavy ions in the three-dimensional stacked structure, the simulation results show that the heavy ion energy can pass through the model of the six-layer die stack after the heavy ion energy is greater than 22MeV/ u, thus it can be seen that each layer in the 3D SRAM may produce soft errors. By using Geant4 simulation to obtain the deposition charge in the sensitive layers of each layer die in the complex three-dimensional stacked structure model, the analysis shows that under the condition of low energy heavy ion bombardment, the soft error characteristics of each layer die are greatly different, but under the condition of high energy heavy ion bombardment, the difference can disappear, and the underlying die is more susceptible to a more severe mcu. It is also found that TSVs have a blocking effect on incident heavy ions, and TSV can reduce the inverted cross section of the surrounding sensitive cells. and (4) constructing a 3D SRAM soft error analysis platform, and analyzing the soft error characteristics of the 3D SRAM. Based on the established SET, SEU simulation method and mature tool, the 3D SRAM soft error analysis platform is established, which can quickly and accurately analyze and evaluate the soft error of 3D SRAM. Based on this platform, soft error analysis of 2D SRAM, word line division 3D SRAM and bit line division 3D SRAM were carried out. The results show that the flip section of the three SRAM is almost the same in the vertical bombardment static test, but the inverted cross section of the 3D SRAM is larger than 2D SRAM in the random incident angle simulation; the word line division 3D SRAM in the static test will produce more serious MBU, Therefore, the bit line division 3D SRAM is more suitable for application in the irradiation environment; the combinational logic circuits of the three SRAM in the dynamic test cause serious MBU; due to the small number of sensitive units around the TSV, the TSV can only reduce the inverted cross section of about 3%.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2016
【分類號】：TP333

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