【摘要】：基于無線節(jié)點(diǎn)的心電信號(hào)檢測正在得到越來越廣泛的應(yīng)用,為了保證檢測設(shè)備的便攜性和易用性,需要設(shè)計(jì)一款低功耗運(yùn)行的心電信號(hào)處理器,以延長設(shè)備的續(xù)航時(shí)間,提升設(shè)備的使用舒適性。本文基于現(xiàn)有商用處理器體系結(jié)構(gòu),面向心電信號(hào)檢測的便攜應(yīng)用需求,針對(duì)處理器的低功耗設(shè)計(jì)方法開展深入研究。通過引入塊指令方法,改變處理器的指令運(yùn)行方式,在不損失處理器靈活性的前提下,在體系結(jié)構(gòu)層面降低處理器功耗,提升心電信號(hào)檢測設(shè)備的續(xù)航。主要內(nèi)容如下：分析典型心電應(yīng)用程序,針對(duì)測試數(shù)據(jù)標(biāo)簽不平衡的現(xiàn)象,引入遷移算法改進(jìn)現(xiàn)有學(xué)習(xí)算法,提升信號(hào)判斷的準(zhǔn)確率。引入塊指令方法優(yōu)化功耗。通過分析心電應(yīng)用匯編指令級(jí)特征：指令聚類多、內(nèi)存訪問集中、核心算法固定、程序流分支少,通過聚合原子操作形成塊指令,改變處理器基于原子指令運(yùn)行的方式,減少處理器取指、譯碼和運(yùn)行時(shí)的功耗。提出基于塊指令的編譯運(yùn)行框架。使用塊指令調(diào)度模塊聚合原子指令優(yōu)化形成塊指令；引入字典壓縮、寄存器重分配、預(yù)先譯碼、同類操作合并等利于硬件低功耗執(zhí)行的技術(shù),在壓縮指令空間的同時(shí),降低處理器運(yùn)行功耗。提出基于塊指令執(zhí)行的處理器架構(gòu)。改進(jìn)現(xiàn)有商業(yè)處理器架構(gòu),以塊為最基本的操作單元完成指令的執(zhí)行,化零為整,優(yōu)化指令操作。引入主動(dòng)內(nèi)存,內(nèi)存主動(dòng)提供待執(zhí)行的指令,驅(qū)動(dòng)處理器完成指令執(zhí)行。主動(dòng)內(nèi)存的引入增強(qiáng)了內(nèi)存的靈活性,減少了總線的傳輸,降低了處理器的設(shè)計(jì)難度,去除了處理器的取指、譯碼邏輯。引入自驅(qū)動(dòng)低功耗運(yùn)算單元。運(yùn)算單元自我驅(qū)動(dòng),主動(dòng)搜索能夠執(zhí)行的指令,簡化處理器發(fā)射邏輯,提升處理器運(yùn)行效率。算術(shù)運(yùn)算單元操作數(shù)長度自適應(yīng),多路數(shù)據(jù)并行運(yùn)算,減少處理器運(yùn)行時(shí)間。引入低功耗內(nèi)存訪問單元。使用存儲(chǔ)載入操作的歷史軌跡預(yù)判即將訪問的內(nèi)存地址,基于熱點(diǎn)行自搜索,追蹤熱點(diǎn)程序,預(yù)先載入高速緩存狀態(tài),去除冗余的內(nèi)存訪問和比較操作。該單元還能根據(jù)歷史信息,判定載入的數(shù)據(jù)是否為常數(shù),緩存常數(shù),減少內(nèi)存訪問。本文提出的塊指令方法,對(duì)于降低處理器功耗具有積極的作用。實(shí)驗(yàn)表明,針對(duì)心電應(yīng)用,基于塊指令的低功耗處理器相對(duì)于傳統(tǒng)處理器可以降低35%-40%左右的功耗。
[Abstract]:ECG detection based on wireless nodes is becoming more and more widely used. In order to ensure the portability and ease of use of the detection equipment, a low power consumption ECG processor is needed to prolong the device's life. Enhance the comfort of the use of equipment. Based on the existing commercial processor architecture and the portable application requirements of ECG signal detection, the low power design method of the processor is deeply studied in this paper. By introducing the block instruction method, the instruction operation mode of the processor is changed, and the processor power consumption is reduced at the architecture level without losing the flexibility of the processor, and the continuance of the ECG detection device is improved. The main contents are as follows: analyze the typical ECG application program and introduce the migration algorithm to improve the existing learning algorithm to improve the accuracy of signal judgment. Block instruction method is introduced to optimize power consumption. By analyzing the characteristics of assembly instruction level in ECG application, such as more instruction clustering, memory access set, fixed core algorithm, less branch of program flow, block instruction formed by aggregation atomic operation, the operation mode of processor based on atomic instruction is changed. Reduce the power consumption of processor fetch, decode, and run time. In this paper, a block instruction based framework for compiling and running is proposed. Using block instruction scheduling module to aggregate atomic instruction optimizes to form block instruction, introducing dictionary compression, register redistribution, pre-decoding, similar operation merging and other techniques which are conducive to low power execution of hardware, while compressing instruction space. Reduce processor running power consumption. A processor architecture based on block instruction execution is proposed. The existing commercial processor architecture is improved to complete instruction execution with block as the most basic operation unit and to optimize instruction operation. Active memory is introduced. Memory actively provides instructions to be executed, driving the processor to complete instruction execution. The introduction of active memory enhances the flexibility of memory, reduces the transmission of bus, reduces the difficulty of processor design, and removes the logic of the processor. Self-driven low power computing unit is introduced. The operation unit is self-driven, actively searches for the instructions that can be executed, simplifies the processor's transmit logic, and improves the processor's running efficiency. The arithmetic operation unit adapts to the Operand length and the multiplex data parallel operation reduces the processor running time. A low power memory access unit is introduced. The memory address to be accessed is predicted by using the historical track of the storage loading operation, based on the hot spot line self-search, tracking the hot spot program, pre-loading the cache state, removing redundant memory access and comparing operations. The unit can also determine whether the loaded data is constant, cache constant and reduce memory access according to historical information. The block instruction method proposed in this paper plays an active role in reducing processor power consumption. Experiments show that the low power processor based on block instruction can reduce the power consumption by 35% to 40% compared with the traditional processor for ECG applications.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2016
【分類號(hào)】：R540.4;TN911.23

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