本文選題：紅外焦平面探測(cè)器芯片 + 微測(cè)輻射熱計(jì)��； 參考：《電子科技大學(xué)》2016年博士論文

【摘要】：非制冷紅外探測(cè)器已廣泛地應(yīng)用于軍事、邊防、消防、工業(yè)檢測(cè)、交通等各個(gè)領(lǐng)域,人們對(duì)于探測(cè)器的性能要求也越來越高;為滿足此要求,開展高性能探測(cè)器芯片研究應(yīng)運(yùn)而生。高性能意味著具有更高信噪比、更高效率,非理想效應(yīng)的自適應(yīng)補(bǔ)償功能;同時(shí)還應(yīng)滿足大陣列、輕質(zhì)量等需求。本論文以完成高性能非制冷紅外探測(cè)器芯片一體化設(shè)計(jì)為目標(biāo),研究了一體化設(shè)計(jì)高性能系統(tǒng)芯片所需的主要關(guān)鍵技術(shù)。所涉及到的關(guān)鍵技術(shù)包括:探測(cè)器像元建模技術(shù)、探測(cè)器溫度補(bǔ)償技術(shù)、探測(cè)器芯片片上ADC技術(shù)、探測(cè)器芯片非均勻性校正技術(shù)、探測(cè)器芯片數(shù)字控制技術(shù)。論文的主要研究內(nèi)容綜述如下:1、研究了微測(cè)輻射熱計(jì)型探測(cè)器像元電學(xué)設(shè)計(jì)平臺(tái)兼容的一體化設(shè)計(jì)模型。通過數(shù)學(xué)推導(dǎo)和參數(shù)仿真,提出了涵蓋器件光-熱-電多物理場(chǎng)特性的線性模型,其可供電學(xué)設(shè)計(jì)平臺(tái)使用,以輔助探測(cè)器系統(tǒng)一體化設(shè)計(jì)。該模型與經(jīng)典模型在探測(cè)器溫度變化40K時(shí)偏差小于5%,具有良好的精度。2、研究了探測(cè)器的溫度補(bǔ)償技術(shù),包含自熱效應(yīng)補(bǔ)償和襯底溫度補(bǔ)償。針對(duì)自熱效應(yīng)提出使用片上電流DAC或片上電阻DAC的方式進(jìn)行補(bǔ)償。針對(duì)襯底溫度導(dǎo)致的非理想效應(yīng)提出引入補(bǔ)償盲像元的方案用于補(bǔ)償襯底溫度的影響。對(duì)于電壓偏置型紅外讀出電路,以采樣運(yùn)放跨阻的形式引入補(bǔ)償盲像元;對(duì)于電流偏置型紅外讀出電路,以積分器積分電阻的形式的引入補(bǔ)償盲像元。利用像元一體化設(shè)計(jì)模型仿真優(yōu)化設(shè)計(jì)。經(jīng)樣片測(cè)試后在溫度變化為80K時(shí),采用所提溫度補(bǔ)償技術(shù)的探測(cè)器的輸出變化率約為20%,其響應(yīng)率變化率約為40%。3、研究了探測(cè)器的片上ADC,包括芯片級(jí)ADC和列級(jí)ADC。首先由使用像元一體化設(shè)計(jì)模型的讀出電路仿真結(jié)果提出片上ADC的性能需求,然后分別研究芯片級(jí)ADC和列級(jí)ADC。在芯片級(jí)ADC方面,以Pipeline ADC為代表展開研究。首先基于Matlab設(shè)計(jì)并開發(fā)了一套Pipeline ADC功耗優(yōu)化結(jié)構(gòu)軟件,并由該軟件確定了兩種低功耗Pipeline ADC結(jié)構(gòu)。然后提出了一種基于擾動(dòng)注入(Dither)和動(dòng)態(tài)元件匹配(Dynamic Element Match,DEM)的數(shù)字后臺(tái)算法,以及一種準(zhǔn)實(shí)時(shí)校準(zhǔn)的數(shù)字前臺(tái)校準(zhǔn)方案,該方案可同時(shí)實(shí)現(xiàn)連續(xù)性校準(zhǔn)和增益校準(zhǔn),并將它們分別應(yīng)用到所提低功耗結(jié)構(gòu)中。由實(shí)物樣品測(cè)試知,使用數(shù)字后臺(tái)算法的Pipeline ADC功耗為299.93mW,DNL為+0.84LSB/-0.94LSB,INL為+0.99LSB/-1.19LSB;而使用數(shù)字前臺(tái)算法的Pipeline ADC功耗為280.96mW,DNL為+0.86LSB/-0.75LSB,INL為+1.53LSB/-1.41LSB。在列級(jí)ADC方面,以Single Slope ADC為代表展開研究。為了提高Single Slope ADC的轉(zhuǎn)換速率,本文提出了半周期計(jì)數(shù)法、兩步比較法以及行劃分法三種方案;為加強(qiáng)Single Slope ADC信號(hào)在探測(cè)器芯片上遠(yuǎn)距離傳輸時(shí)的準(zhǔn)確性,提出了電流傳輸方案,避免信號(hào)誤碼。通過將補(bǔ)償盲像元引入ADC參考電壓的產(chǎn)生電路,獲得了具有溫度補(bǔ)償功能的Single Slope ADC,該結(jié)構(gòu)可稱為數(shù)字溫度補(bǔ)償結(jié)構(gòu)。通過樣品測(cè)試,單個(gè)該Single Slope ADC實(shí)際21.86mW,估算其應(yīng)用于1280×1024陣列時(shí)的總功耗為290.19mW,DNL為+0.72LSB/-0.71LSB,INL為+1.18LSB/-1.09LSB。當(dāng)襯底溫度變化80K時(shí),輸出數(shù)字碼658個(gè)數(shù)字碼,占數(shù)字動(dòng)態(tài)范圍的16.1%,響應(yīng)率變化率為40.6%。4、研究了探測(cè)器的非均勻校正方案,針對(duì)本論文重點(diǎn)研究的三種讀出電路結(jié)構(gòu)分別提出了非均勻性校正方案以及流程。對(duì)于電壓偏置結(jié)構(gòu)、電流偏置結(jié)構(gòu),本論文提出以片上電壓DAC調(diào)節(jié)它們的跨阻運(yùn)放參考電壓,從而實(shí)現(xiàn)一點(diǎn)溫度補(bǔ)償。針對(duì)該方法設(shè)計(jì)了一種精度和范圍可調(diào)的片上電壓DAC,該DAC具有4種電壓調(diào)節(jié)范圍。由樣片測(cè)試,電壓偏置結(jié)構(gòu)的FNP可降低為11.8mV,電流偏置結(jié)構(gòu)的FNP被降低到10.4mV。對(duì)于數(shù)字溫度補(bǔ)償結(jié)構(gòu),本論文提出使用兩個(gè)片上電流DAC調(diào)節(jié)其偏置電流,從而實(shí)現(xiàn)兩點(diǎn)溫度補(bǔ)償。由樣片測(cè)試,溫度補(bǔ)償ADC結(jié)構(gòu)的FNP為127.3mV。5、在數(shù)字控制技術(shù)方面,研究了陣列掃描方式、幀信號(hào)和逐點(diǎn)校正信號(hào)的輸入方案以及讀出結(jié)果的輸出方案。將電壓偏置結(jié)構(gòu)+Single Slope ADC的ROIC在640×512的陣列下設(shè)計(jì)制作了大陣列探測(cè)器芯片,性能測(cè)試結(jié)果為平均響應(yīng)率為8.83codes/K,約為7.33mV/K;RMS噪聲為325.3μV,FPN噪聲為12.1mV,NETD為62.33mK。
[Abstract]:Uncooled infrared detectors have been widely used in various fields such as military, border defense, fire protection, industrial detection and transportation, and the performance requirements of detectors are becoming higher and higher. In order to meet this requirement, high performance detector chip research has been developed. High performance means that it has higher signal-to-noise ratio, more efficient and non ideal effect. In order to complete the design of high performance uncooled infrared detector chip integrated design, the main key technologies needed for integrated design of high performance system chip are studied in this paper. The key technologies involved include: detector pixel modeling technology, detector temperature supplement The compensation technology, the ADC technology on the chip chip, the non uniformity correction technology of the detector chip and the digital control technology of the detector chip are summarized as follows: 1, the integrated design model of the compatible design platform of the micrometer radiation thermeter type detector is studied. The culvert is put forward by mathematical deduction and parameter simulation. A linear model of the characteristics of the multi physical field of light and thermal electric field, which can be used to assist the integrated design of the detector system. The model and the classic model have a deviation of less than 5% and a good precision.2 when the temperature change of the detector is 40K. The temperature compensation technique of the detector is studied, including the self thermal effect compensation and the substrate temperature. To compensate for the self heat effect, the use of the on-chip current DAC or the on-chip resistance DAC is proposed. The compensation blind pixel scheme is introduced to compensate the influence of the substrate temperature for the non ideal effect caused by the substrate temperature. For the current biased infrared readout circuit, the compensation blind pixel is introduced in the form of integrator integral resistance. The design model of the pixel integration is used to simulate the optimization design. When the temperature change is 80K, the output change rate of the detector using the proposed temperature compensation technique is about 20%, and the response rate is about 40%.3. The on-chip ADC of the detector, including chip level ADC and column level ADC., is first proposed by the read-out circuit simulation results using the pixel integrated design model, and then the chip level ADC and the column level ADC. are studied respectively in the chip level ADC, and Pipeline ADC is considered as the representative. First, the design and development of the Pipeline ADC are designed and developed on Matlab. A set of Pipeline ADC power optimization structure software is used to determine two kinds of low power Pipeline ADC structures. Then a digital background algorithm based on disturbance injection (Dither) and dynamic component matching (Dynamic Element Match, DEM) is proposed, and a quasi real-time calibration scheme of digital front desk is proposed. The scheme can be implemented simultaneously. Continuous calibration and gain calibration are applied to the proposed low power structure. The Pipeline ADC power consumption of the digital background algorithm is 299.93mW, the DNL is +0.84LSB/-0.94LSB, and the INL is +0.99LSB/-1.19LSB, while the Pipeline ADC power consumption of the digital front algorithm is 280.96mW and DNL is +0.86LSB/-0.75LSB. In order to improve the conversion rate of Single Slope ADC, L is the representative of +1.53LSB/-1.41LSB. in the column level ADC. In order to improve the conversion rate of Single Slope ADC, this paper proposes a semi periodic counting method, two step comparison method and three schemes of line division, and the accuracy of enhancing the long distance transmission of Single Slope ADC signal on the probe chip. The current transmission scheme avoids the signal error code. By introducing the compensation blind pixel into the ADC reference voltage generating circuit, the Single Slope ADC with the temperature compensation function is obtained. The structure can be called the digital temperature compensation structure. The total work of the 1280 * 1024 array is estimated by the sample test and the actual 21.86mW of the single Single Slope ADC. The consumption is 290.19mW, DNL is +0.72LSB/-0.71LSB, INL is +1.18LSB/-1.09LSB. when the substrate temperature changes 80K, the output digital code is 658 digital codes, which accounts for 16.1% of the digital dynamic range and the response rate change rate is 40.6%.4. The non uniform correction scheme of the detector is studied. The non uniformity of the three readout circuit structures which are mainly studied in this paper are put forward respectively. The uniformity correction scheme and process. For voltage bias structure and current bias structure, this paper proposes to adjust their cross resistance amplifier reference voltage by DAC on chip voltage to achieve a point of temperature compensation. In this method, a precision and range adjustable voltage DAC is designed for this method. The DAC has 4 range of voltage regulation. The voltage bias structure of the FNP can be reduced to 11.8mV, the FNP of the current bias structure is reduced to the 10.4mV. for digital temperature compensation structure. This paper proposes to use two on-chip current DAC to adjust its bias current to achieve two point temperature compensation. The input scheme of the array scanning, the frame signal and the point by point correction signal and the output scheme of the readout result are studied. A large array detector chip is designed and produced by the voltage biased structure of +Single Slope ADC under 640 x 512 array. The performance test result is that the average response rate is 8.83codes/K, about 7.33mV/K, and the RMS noise is 325.3. V, FPN noise is 12.1mV, NETD is 62.33mK.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN215

【參考文獻(xiàn)】

相關(guān)期刊論文 前4條

1 雷亞貴;王戎瑞;陳苗海;;國外非制冷紅外焦平面陣列探測(cè)器進(jìn)展[J];激光與紅外;2007年09期

2 石巖,張?zhí)煨?李輝,曹治國;一種考慮紅外焦平面器件非線性響應(yīng)的非均勻性校正方法[J];紅外與毫米波學(xué)報(bào);2004年04期

3 王多加,周向陽,金同銘,胡祥娜,鐘嬌娥,吳啟堂;近紅外光譜檢測(cè)技術(shù)在農(nóng)業(yè)和食品分析上的應(yīng)用[J];光譜學(xué)與光譜分析;2004年04期

4 王宏臣,易新建,陳四海,黃光,肖靜;128元非致冷氧化釩紅外探測(cè)器的制作[J];紅外與毫米波學(xué)報(bào);2004年02期

相關(guān)博士學(xué)位論文 前6條

1 楊波;可見拓展的短波紅外InGaAs探測(cè)器研究[D];中國科學(xué)院研究生院（上海技術(shù)物理研究所）;2014年

2 梁上泉;流水線模數(shù)轉(zhuǎn)換器偽隨機(jī)序列注入后臺(tái)快速數(shù)字校準(zhǔn)技術(shù)研究[D];合肥工業(yè)大學(xué);2011年

3 楊e，

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