本文選題：ESD + 高壓ESD防護(hù)　； 參考：《湖南大學(xué)》2016年博士論文

【摘要】：靜電放電(ESD)是造成集成電路失效的主要原因之一。研究ESD機(jī)理并采用適當(dāng)有效的方法防止損害發(fā)生對集成電路的可靠性有重大影響。隨著微電子行業(yè)的發(fā)展,集成電路的ESD保護(hù)面臨越來越大的挑戰(zhàn)。對集成電路的ESD可靠性進(jìn)行研究,采取有效措施對集成電路芯片進(jìn)行ESD保護(hù),具有重要的理論意義和實(shí)際價(jià)值。本文對集成電路芯片內(nèi)高壓ESD保護(hù)器件進(jìn)行深入研究。采用互補(bǔ)型和雙擴(kuò)散型(CDMOS)制造工藝,流片制備了三種不同形狀的高壓N溝道橫向擴(kuò)散MOS的ESD器件,采用傳輸線脈沖測試(TLP)系統(tǒng)測試器件的性能參數(shù),結(jié)果顯示,方型版圖結(jié)構(gòu)的電流能力比傳統(tǒng)的叉指型和八角型分別增加30%和25%以上,具有高的魯棒性,低的漏電流特性和高的電流放電效率。采用0.5微米5V/18VCDMOS工藝流片兩組可控硅整流(SCR)ESD器件,使用TLP系統(tǒng)測試器件的性能參數(shù),結(jié)果表明,LDMOS-SCRESD器件的維持電壓隨著N阱內(nèi)P+區(qū)和P阱內(nèi)N+區(qū)間距線性增大,而單位面積的失效電流線性減小。擬合維持電壓和單位面積失效電流隨間距變化的解析表達(dá)式,得到與實(shí)際一致的結(jié)果。采用軟件仿真,獲取單向LDMOS-SCRESD器件工作時(shí)I-V曲線,結(jié)果顯示,器件的漂移區(qū)長度增加提高器件的失效電流但降低維持電壓。提取關(guān)鍵點(diǎn)的少數(shù)載流子濃度、電流密度、電壓強(qiáng)度等電學(xué)特性參數(shù),分析得出內(nèi)部載流子輸運(yùn)能力增強(qiáng),但導(dǎo)通電阻無明顯變化是該現(xiàn)象的內(nèi)在原因。流片測試結(jié)果驗(yàn)證了仿真結(jié)果的正確性。雙向高壓DDSCR器件由兩個(gè)單向SCR結(jié)構(gòu)器件構(gòu)成,研究發(fā)現(xiàn)DDSCR器件內(nèi)對應(yīng)于單向SCR結(jié)構(gòu)器件漂移區(qū)的區(qū)域長度與器件性能有關(guān)。區(qū)域長度大,維持電壓高,ESD保護(hù)水平降低;反之亦然。提出了一種新型的ESD保護(hù)器件(M-ESD器件),該器件內(nèi)部憶阻器與寄生晶體管組成的系統(tǒng)能夠有效地協(xié)同工作,在不增大芯片面積和不降低維持電壓的情況下,使器件的失效電流增加,提高器件的保護(hù)水平。為了獲得適合于M-ESD器件的憶阻元件,研究了納米級器件Ag/MoSe2/Au的憶阻屬性,采用水熱法合成了MoSe2納米樣品,由光刻制作電極,器件顯示出良好的雙極電阻開關(guān)行為和較低的工作電壓。本文對片外ESD保護(hù)壓敏電阻進(jìn)行了研究。提出了一種新型抗沖擊老化的ZnO壓敏陶瓷ESD器件,增加Pr_(0.1)Ca_(0.9)MnO_3陶瓷層,用于提高壓敏電阻多次擊穿后的抗老化能力。采用固相燒結(jié)方法制備了Pr_(1-x)Ca_xMnO_3(x=0.1)陶瓷樣品,對樣品在磁場和電場下直流、交流輸運(yùn)性質(zhì)的研究表明,其電阻可分為晶粒體電阻與晶界電阻兩部分,特性差異明顯。同時(shí)測量了樣品在不同頻率下的阻抗溫譜,擬合得出勢壘高度與用直流R-T數(shù)據(jù)得出的激活能一致。提出一種新型抗寄生電容干擾的ZnO壓敏ESD器件,制備了BiMnO_(3+δ)樣品作為新型器件的憶阻材料,研究納米級器件Ag/BiMnO_(3+δ)/Ag的憶阻屬性。結(jié)果表明,Ag/BiMnO_(3+δ)/Ag器件的關(guān)/開電阻率達(dá)10,并且具有很好的穩(wěn)定性。本文還對防靜電材料進(jìn)行研究,采用電化學(xué)沉積的方法,在銅襯底上制備一層硫化亞銅樣品,在樣品和銅襯底上濺射銀電極,通過測試電輸運(yùn)特性研究硫化亞銅材料的憶阻特性,結(jié)果表明三明治結(jié)構(gòu)的Ag/Cu_2S/Ag結(jié)構(gòu)具有較高的憶阻效應(yīng),進(jìn)一步利用該特性進(jìn)行了防靜電指示功能設(shè)計(jì)。
[Abstract]:Electrostatic discharge (ESD) is one of the main causes of the failure of integrated circuits. The study of the mechanism of ESD and the use of appropriate and effective methods to prevent the occurrence of damage have a significant impact on the reliability of integrated circuits. With the development of the microelectronics industry, the ESD protection of integrated circuits is facing more and more challenges. The reliability of the integrated circuits is studied, and the reliability of the integrated circuits is studied. It is of great theoretical significance and practical value to take effective measures for ESD protection of integrated circuit chips. In this paper, the high voltage ESD protection devices in integrated circuit chips are studied in depth. Using complementary and double diffusion (CDMOS) manufacturing technology, three kinds of ESD devices with different shapes of high voltage N channel transverse diffusion MOS are prepared. The transmission line pulse test (TLP) system is used to test the performance parameters of the device. The results show that the current capacity of the square pattern structure is increased by 30% and 25% more than the traditional interdigital and octagonal type. It has high robustness, low leakage current characteristics and high current discharge efficiency. 0.5 micron 5V/18VCDMOS process sheets are used to complete the silicon control. A flow (SCR) ESD device is used to test the performance parameters of the device using the TLP system. The results show that the maintenance voltage of the LDMOS-SCRESD device is linearly increased with the N+ zone spacing in the P+ region and the P well in the N well, and the failure current of the unit area is linearly reduced. The analytical expression of the fitting maintenance voltage and the unit area failure current with the distance is obtained. The result shows that the I-V curve of the unidirectional LDMOS-SCRESD device is obtained by software simulation. The result shows that the drift region length of the device is increased and the failure current of the device is increased, but the maintenance voltage is reduced. The parameters of the minority carrier concentration, current density and voltage intensity are extracted at the key point, and the internal carrier transport capacity is analyzed. The inner reason of the phenomenon is no obvious change in the conduction resistance. The flow test results verify the correctness of the simulation results. The bidirectional high voltage DDSCR device is composed of two unidirectional SCR structure devices. It is found that the length of the drift region corresponding to the unidirectional SCR structure device is related to the device performance. The length of the region is large and the dimension of the region is large. High voltage and lower ESD protection level, and vice versa. A new type of ESD protection device (M-ESD device) is proposed. The system composed of internal memristor and parasitic transistor can work effectively, increasing the failure current of the device without increasing the chip area and maintaining the maintenance voltage, and improving the protection of the device. In order to obtain the memristor elements suitable for M-ESD devices, the memristor properties of the nanoscale device Ag/MoSe2/Au are studied. The MoSe2 nano samples are synthesized by hydrothermal method. The electrodes are made by photolithography. The devices show good bipolar resistance switching behavior and low working voltage. This paper studies the ESD protective varistor in this paper. A new type of anti impact aging ZnO varistor ceramic ESD device was developed to increase the Pr_ (0.1) Ca_ (0.9) MnO_3 ceramic layer to improve the anti-aging ability of the varistor after multiple breakdown. A solid phase sintering method was used to prepare Pr_ (1-x) Ca_xMnO_3 (x=0.1) ceramics samples. The study on the AC transport properties of samples under magnetic field and electric field and the AC transport properties were studied. The resistance can be divided into two parts, grain resistance and grain boundary resistance. The characteristic difference is obvious. At the same time, the impedance temperature spectrum of the sample at different frequencies is measured. The height of the barrier is fitted to the activation energy obtained by the direct current R-T data. A new type of ZnO piezoelectric ESD device with a new anti parasitic capacitance interference is proposed, and the BiMnO_ (3+ delta) sample is prepared as a new sample. The memristor of the type device is used to study the memory resistance properties of the nano scale device Ag/BiMnO_ (3+ delta) /Ag. The results show that the close / open resistivity of Ag/BiMnO_ (3+ delta) /Ag device is 10 and has good stability. In this paper, the antistatic material was studied and a layer of copper sulfide samples was prepared on the copper substrate by electrochemical deposition. By sputtering the silver electrode on the copper substrate, the memristor characteristics of the copper sulfide materials are studied by measuring the electrical transport properties. The results show that the Ag/Cu_2S/Ag structure of the sandwich structure has a high recristor effect. Further use of this characteristic is used to design the anti static function.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2016
【分類號】：TN402

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