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基于槽技術的SOI LDMOS器件新結構研究

發(fā)布時間:2018-05-11 07:48

  本文選題:絕緣體上硅 + 槽柵; 參考:《天津大學》2016年博士論文


【摘要】:作為SOI(Silicon On Insulator)功率集成電路的核心器件,SOI LDMOS(Lateral Double-diffused MOSFET)器件因具有低功耗、易于集成、速度快等優(yōu)勢被廣泛應用于航空航天、無線通信、汽車電子等領域。提高器件耐壓和降低器件比導通電阻是功率器件設計中非常重要的兩個方面。對于傳統(tǒng)SOI LDMOS器件,提高擊穿電壓的同時往往伴隨著比導通電阻的增加。本文以緩解擊穿電壓和比導通電阻的矛盾關系為目的,對基于槽技術的SOI LDMOS器件結構進行了深入研究。在深入研究槽柵SOI結構、槽漏SOI結構以及雙槽型SOI結構的擊穿特性和比導通電阻特性的基礎上,本文提出了三種基于槽技術的SOI LDMOS器件新結構:具有縱向漏極場板的槽柵槽漏SOI LDMOS器件新結構、具有L型源極場板的雙槽型SOI LDMOS器件新結構、具有縱向柵極場板的槽柵槽源SOI LDMOS器件新結構。二維數(shù)值仿真結果表明,本論文提出的三種新結構能夠緩解擊穿電壓與比導通電阻的矛盾關系。本論文的主要創(chuàng)新工作包括:1、提出了一種具有縱向漏極場板的槽柵槽漏SOI LDMOS器件新結構。該結構采用了槽柵槽漏結構,降低了器件比導通電阻;漏端采用了縱向漏極場板,該場板對漏端下方的電場進行了調制,減弱了漏極末端的高電場,提高了器件耐壓。與傳統(tǒng)SOI結構相比,擊穿電壓提高了4%,比導通電阻降低了53%。2、提出了一種具有L型源極場板的雙槽型SOI LDMOS器件新結構。漂移區(qū)引入的槽型介質層顯著提高了器件擊穿電壓,在L型源極場板的作用下,比導通電阻顯著下降。與相同器件尺寸的傳統(tǒng)SOI結構相比,擊穿電壓提高了151%,比導通電阻降低了20%。與相同擊穿電壓的傳統(tǒng)SOI結構相比,比導通電阻降低了80%。3、提出了一種具有縱向柵極場板的槽柵槽源SOI器件新結構。槽柵槽源結構擴展了電流傳導區(qū)域,降低了器件比導通電阻。縱向柵極場板及右側氧化層使該結構具有更高的耐壓。與傳統(tǒng)SOI結構相比,擊穿電壓提高了33%,比導通電阻降低了33%。
[Abstract]:As the core device of SOI(Silicon on Insulator power integrated circuit, the SOI LDMOS(Lateral Double-diffused MOSFET device has been widely used in aerospace, wireless communication, automotive electronics and other fields because of its advantages of low power consumption, easy integration, high speed and so on. It is very important to improve the voltage resistance and reduce the specific on-resistance of power devices. For conventional SOI LDMOS devices, increasing breakdown voltage is often accompanied by an increase in specific on-resistance. In order to alleviate the contradiction between breakdown voltage and specific on-resistance, the structure of SOI LDMOS device based on slot technology is studied in this paper. On the basis of deeply studying the breakdown characteristics and specific on-resistance characteristics of groove-gate SOI structure, groove-drain SOI structure and double-slot SOI structure, In this paper, three new structures of SOI LDMOS devices based on slot technology are proposed: a new structure of slot gate drain SOI LDMOS device with longitudinal drain field plate and a new structure of double slot type SOI LDMOS device with L source pole field plate. A new structure of grooved gate source SOI LDMOS device with longitudinal gate field plate. The results of two-dimensional numerical simulation show that the three new structures proposed in this paper can alleviate the contradiction between breakdown voltage and specific on-resistance. The main innovation work of this thesis includes: 1. A new structure of slot gate slot leakage SOI LDMOS device with longitudinal drain field plate is proposed. In this structure, the slot gate drain structure is adopted to reduce the specific on-resistance of the device, and the longitudinal drain field plate is used at the drain end, which modulates the electric field below the drain end, which weakens the high electric field at the drain end and improves the device voltage. Compared with the traditional SOI structure, the breakdown voltage is increased by 4% and the on-resistance is reduced by 53.2. A new structure of double-slot SOI LDMOS device with L source pole field plate is proposed. The dielectric layer in the drift region increases the breakdown voltage of the device, and the specific on-resistance decreases significantly under the action of the L-type source field plate. Compared with the conventional SOI structure with the same device size, the breakdown voltage is increased by 151% and the on-resistance is reduced by 20%. Compared with the conventional SOI structure with the same breakdown voltage, the specific on-resistance is reduced by 80. 3. A new structure of grooved gate source SOI device with longitudinal gate field plate is proposed. The groove-gate source structure expands the current conduction area and reduces the specific on-resistance of the device. The longitudinal gate field plate and the right oxide layer make the structure have higher voltage resistance. Compared with the traditional SOI structure, the breakdown voltage is increased by 33% and the on-resistance is reduced by 33%.
【學位授予單位】:天津大學
【學位級別】:博士
【學位授予年份】:2016
【分類號】:TN386

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