本文選題：深納米CMOS工藝 + 寄生效應(yīng)波動性��； 參考：《華東師范大學》2016年博士論文

【摘要】：CMOS工藝特征尺寸的等比例減小使得器件尺寸、接觸孔邊長與間距、互連線線寬與間距縮小至深納米數(shù)量級,進而導致MOS器件柵結(jié)構(gòu)周圍、多層互連線的寄生電容與電阻等寄生效應(yīng)日趨嚴重,器件柵圍和互連線的寄生效應(yīng)所產(chǎn)生的延時遠遠超過了器件的本征延時,對高速電路設(shè)計中時序分析、功耗分析、信號完整性設(shè)計等帶來了巨大挑戰(zhàn)。因此,準確描述CMOS工藝的各種寄生效應(yīng)及其波動性、并實現(xiàn)深納米電路仿真的精準模型至關(guān)重要。本論文以深納米工藝代CMOS技術(shù)所產(chǎn)生的寄生效應(yīng)及其波動性為研究對象,意圖深入分析并建立前端MOSFET非本征柵圍寄生電容模型、柵電阻模型及與工藝波動相關(guān)的后端多層互連線寄生電容和電阻模型。論文工作中自主設(shè)計并制造了深納米工藝代的寄生電容與電阻測試結(jié)構(gòu),建立了基于電學數(shù)據(jù)(Silicon Data)的模型建立和參數(shù)提取流程,自主實現(xiàn)了SPICE模型和互連線工藝格式(Interconnect Technology Format, ITF)文件的擴充和優(yōu)化。基于上述目標,本論文的工作可以概括為以下四項：一、針對MOSFET非本征部分的柵圍寄生電容,本論文基于40nm CMOS工藝,重點研究了多晶硅柵至接觸孔距離(Contact to Poly Space,縮寫CPS)、接觸孔至接觸孔距離(Contact to Contact Space,縮寫CCS)變化對柵至源/漏邊緣電容Cf及其波動性的影響。工作中,自主設(shè)計并流片制備了25個CCS和CPS尺寸的Gate-Poly測試結(jié)構(gòu)及Field-Poly去嵌結(jié)構(gòu)。分析測試所得電學數(shù)據(jù)表明,Cf的波動具有較明顯的版圖布局相關(guān)性,在CPS和CCS接近設(shè)計規(guī)則允許的最小尺寸下有將近200%的波動。通過對電學數(shù)據(jù)的分析,本論文建立了Cf版圖布局效應(yīng)的SPICE模型與參數(shù)提取流程,對電學數(shù)據(jù)達到了5%的擬合,并且對模型進行了準確的驗證。二、針對MOSFET柵圍寄生電阻,本論文基于40nm CMOS工藝,提出了多晶硅柵電阻的模型拓撲結(jié)構(gòu),重點研究了多晶硅柵電阻的非線性效應(yīng)的模型,包括溫度與偏壓特性、寄生電容特性。工作中,通過42個不同尺寸的N+、P+開爾文(Kelvin)柵電阻測試結(jié)構(gòu)的電學數(shù)據(jù),對溫度相關(guān)特性(Temperature-Dependent Characteristics, TDC)、溫度相關(guān)的偏壓次級效應(yīng)TDVC (Temperature-Dependent Voltage Characteristics)、以及柵與襯底耦合寄生電容進行了準確建模和參數(shù)提取。三、針對多層互連工藝,本論文重點研究了化學機械拋光(Chemical Mechanical Polish, CMP)、光學鄰近修正(Optical Proximity Correction, OPC)等工藝波動對寄生效應(yīng)的影響,本文基于55nm l P4M工藝自主設(shè)計了1種在片(On Wafer)測試電路、3類模型測試結(jié)構(gòu)、1類模型校準結(jié)構(gòu)。其中,在片測試電路基于CIEF CBCM測試方法(Charge-injection-induced Error-free Charge-based Capacitance Measurement),由不交疊的信號驅(qū)動進行兩步測量,扣除了測試電路中的寄生參量,使測試精度到達0.1fF級別,待測電容面積縮小至傳統(tǒng)大面積電容結(jié)構(gòu)的1/160。模型測試結(jié)構(gòu)和校準結(jié)構(gòu)包括：1、不同線寬(Width)和線間距(Space)的同層金屬互連線耦合寄生電容測試結(jié)構(gòu)。2、不同Width和Space的層間金屬互連線覆蓋寄生電容測試結(jié)構(gòu)。3、不同Width和不同Space的多層金屬寄生電容校準結(jié)構(gòu)。4、不同Width和Space的單層四端開爾文金屬互連線寄生電阻測試結(jié)構(gòu)。四、針對多層互連工藝,不同于器件效應(yīng)的SPICE建模,本論文建立版圖寄生參數(shù)(Layout Parasitic Extraction, LPE)流程,通過完善反應(yīng)局部波動性的典型(Typical)文件和反應(yīng)全局波動性的角(Corner) ITF文件,對互連工藝寄生效應(yīng)進行建模。在對典型ITF校準中,通過比對測試所得的電學數(shù)據(jù),代工廠所提供的基礎(chǔ)典型ITF的電容與電阻提取值誤差十分明顯,同層金屬互連線耦合寄生電容誤差普遍超過20%,最大誤差達到60%；層間金屬互連線覆蓋寄生電容誤差普遍在5%-15%之間；同層金屬互連線寄生電阻誤差普遍在20%-50%之間。為了減少典型ITF的提取誤差,本文建立基于電學數(shù)據(jù)的典型ITF文件完善流程,使得最終典型ITF文件的所有待測結(jié)構(gòu)提取值與電學數(shù)據(jù)誤差小于5%。在對工藝角(Corner)ITF的校準中,校準全局互連線及電介質(zhì)層形變波動的3G,使測試值區(qū)間位于提取值范圍之間。本文工作所得到的典型ITF與角ITF提取精度及范圍均符合半導體產(chǎn)業(yè)技術(shù)要求。本文基于國有深納米工藝平臺,自主建立并完善了深納米CMOS工藝寄生效應(yīng)波動性的模型及參數(shù)提取流程,取得突出成果如下：I、自主設(shè)計了40nm工藝的柵圍寄生電容Cf待測結(jié)構(gòu)與去嵌結(jié)構(gòu),創(chuàng)造性的提出了Cf版圖布局效應(yīng),并自主建立了相應(yīng)的SPICE模型和參數(shù)提取流程,能夠在電路仿真中準確的評估MOSFET柵圍寄生電容的版圖布局效應(yīng)對器件的影響。取得工作成果發(fā)表于SCI檢索期刊Solid-State Electronics。2、自主創(chuàng)建了40nm工藝的多晶硅柵電阻的溫度與偏壓特性建模流程,描述了多晶硅柵電阻的非線性效應(yīng),建立的SPICE模型能夠準確的評估多晶硅柵電阻在電路中的影響。取得工作成果發(fā)表于EI檢索會議International Conference on Engineering Technology and Application (2015)。3、自主設(shè)計了55nm工藝的金屬互連線測試結(jié)構(gòu)和測試電路,創(chuàng)建了基于電學數(shù)據(jù)的ITF矩陣單元調(diào)整策略和參數(shù)提取流程,完善了典型ITF以及角ITF文件。本工作最終完善的ITF不僅僅提取精度達到產(chǎn)業(yè)界要求,同時對后道互連工藝參數(shù)調(diào)整和高端芯片后端布局布線都有重要的指導意義。取得工作成果發(fā)表于SCI檢索期刊IEEE Electron Devices Letters。
[Abstract]:The equal proportion of the characteristic size of the CMOS process reduces the size of the device, the length and the distance of the contact hole, the line width and spacing of the interconnect line to the deep nanoscale order of magnitude, and then the parasitic effects of the parasitic capacitance and resistance of the multi-layer interconnects are becoming increasingly serious, and the delay of the parasitism of the gate and interconnects in the MOS device is caused by the increase of the line width and spacing of the interconnect lines. Far more than the intrinsic delay of the device, it has brought great challenges to the timing analysis, power analysis and signal integrity design in high speed circuit design. Therefore, it is very important to accurately describe the various parasitic effects and the volatility of the CMOS process, and to realize the precise model of the deep nanoscale circuit simulation. This paper uses the deep nano technology to replace the CMOS technology. The parasitic effect and its fluctuation are studied. The purpose of this study is to analyze and establish the front MOSFET non eigengate parasitic capacitance model, the gate resistance model and the parasitic capacitance and resistance model of the back-end multilayer interconnects, which are related to the process fluctuation. The model building and parameter extraction process based on electrical data (Silicon Data) are established and the SPICE model and the interconnect process format (Interconnect Technology Format, ITF) file are expanded and optimized independently. Based on the above objectives, the work of this paper can be summarized as following four items: 1, non intrinsic to MOSFET Part of the gate enclosure parasitic capacitance, based on the 40nm CMOS process, this paper focuses on the study of the influence of the distance between the polysilicon gate to the contact hole distance (Contact to Poly Space, abbreviated CPS), the contact hole to the contact hole distance (Contact to Contact Space, abbreviated CCS) changes on the gate to source / leakage edge capacitance and its fluctuation. 25 CCS and CPS size Gate-Poly test structures and Field-Poly inlay structures. Analysis and test electrical data show that Cf fluctuations have a more obvious layout correlation, and there are nearly 200% fluctuations in the minimum size allowed by the design rules of the CPS and CCS. Through the analysis of the electrical data, the paper establishes the Cf Edition The SPICE model and parameter extraction process of the local effect are fitted to 5% of the electrical data, and the model is verified accurately. Two, based on the MOSFET grid parasitic resistance, the model topology of the polysilicon gate resistance is proposed based on the 40nm CMOS process, and the nonlinear effect model of the polysilicon gate resistance is focused on. Including temperature and bias characteristics, parasitic capacitance characteristics. In work, electrical data of 42 different sizes of N+, P+ Kelvin (Kelvin) gate resistance test structure, temperature dependent properties (Temperature-Dependent Characteristics, TDC), temperature dependent bias voltage secondary effect TDVC (Temperature-Dependent Voltage Characteristics), Accurate modeling and parameter extraction of the coupling parasitic capacitance between the gate and the substrate. Three, in this paper, the effects of Chemical Mechanical Polish (CMP), optical proximity correction (Optical Proximity Correction, OPC) on parasitic effects are studied in this paper, based on the 55nm L P4M process. The main design of 1 On Wafer test circuit, 3 type of model test structure, 1 class model calibration structure, in which the chip test circuit based on the CIEF CBCM test method (Charge-injection-induced Error-free Charge-based Capacitance Measurement), the non overlapping signal drive to carry out two steps, deducted the parasitism in the test circuit The test precision reaches the 0.1fF level, and the 1/160. model test structure and the calibration structure of the capacitance area to be reduced to the traditional large area capacitance structure include: 1, different Xian Kuan (Width) and line spacing (Space) of the same layer metal interconnect coupling parasitic capacitance test structure.2, the interlayer metal interconnects of different Width and Space cover parasitism. Capacitance test structure.3, different Width and different Space multi-layer metal parasitic capacitance calibration structure.4, different Width and Space single layer four terminal Kelvin metal interconnect parasitic resistance test structure. Four, for multi-layer interconnect process, different from the device effect of SPICE modeling, this paper establishes the layout parasitic parameters (Layout Parasitic Extraction,) LPE) process, modeling the parasitic effect of interconnect process by improving the typical (Typical) file and the global wave Corner ITF file that reacts the local volatility. In the typical ITF calibration, through the electrical data compared with the test, the error of the capacitance and resistance extraction value of the base typical ITF for the generation factory is very low. It is obvious that the parasitic capacitance error of the interconnect line of the same layer is generally more than 20% and the maximum error reaches 60%. The error of interlayer metal interconnect covering parasitic capacitance is generally between 5%-15%, and the parasitic resistance error of the interconnect line of the same layer is generally between 20%-50%. In order to reduce the extraction error of the typical ITF, this paper establishes the typical electrical data. The ITF file consummate the process, making the final typical ITF file of all the measured structure extraction value and electrical data error less than 5%. in the calibration of the process angle (Corner) ITF, calibrate the global interconnect and the dielectric layer deformation fluctuation 3G, make the test value interval between the extracted value range. The typical ITF and corner ITF extraction precision obtained in this work The degree and range are all in accordance with the technical requirements of the semiconductor industry. Based on the state-owned deep nano technology platform, the model and parameter extraction process of the parasitic effect of the deep nano CMOS process are established and perfected independently. The outstanding achievements are as follows: I, the design of the 40nm process of the grid parasitic capacitance Cf to be measured and inlaid structure, and the creativity of the structure are created independently. The layout effect of Cf layout is put forward, and the corresponding SPICE model and parameter extraction process are established independently. The effect of layout effect of MOSFET gate parasitic capacitance on the device can be accurately evaluated in the circuit simulation. The results of the work are published in the SCI retrieval Journal Solid-State Electronics.2, and the polycrystalline 40nm process is created independently. The modeling process of the temperature and bias characteristic of the silicon grid resistors describes the nonlinear effect of the polysilicon gate resistance. The SPICE model can accurately evaluate the influence of the polysilicon grid resistance in the circuit. The results are published in the EI retrieval conference International Conference on Engineering Technology and Application (2015).3, autonomous The metal interconnect test structure and test circuit of 55nm process are designed, the ITF matrix unit adjustment strategy and parameter extraction process based on electrical data are created, the typical ITF and the corner ITF files are perfected. The final perfect ITF not only achieves the industrial requirements, but also adjusts the technological parameters of the post channel interconnect and high end. The back-end layout and routing of chips has important guiding significance. The results obtained are published in the SCI search Journal IEEE Electron Devices Letters..

【學位授予單位】：華東師范大學
【學位級別】：博士
【學位授予年份】：2016
【分類號】：TN405

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