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面向片上光互連的高速光集成芯片研究

發(fā)布時間:2018-04-15 04:13

  本文選題:光子集成 + 片上光互連; 參考:《浙江大學(xué)》2015年博士論文


【摘要】:隨著信息和通信技術(shù)的發(fā)展,人們對于通信網(wǎng)絡(luò)的傳輸、高性能計算機和高端服務(wù)器提出了更高的要求。光集成技術(shù)憑借其體積小、低能耗、大帶寬等優(yōu)點,在光互連、光通信等領(lǐng)域獲得越來越多的青睞。在降低成本和提高性能的愿望驅(qū)使下,集成光電子器件朝著更高集成度的方向不斷發(fā)展。一方面具有采用高折射率差的硅波導(dǎo)減小尺寸;另一方面,將所有光功能以單片或者混合集成的方式整合在硅基材料;诠杌墓庾蛹呻娐凡粌H具有超高帶寬、超快傳輸速率、抗電磁干擾和低能耗等優(yōu)勢,還與CMOS工藝兼容,使得超緊湊的光子集成系統(tǒng)成為可能。在諸如芯片間、芯片內(nèi)部采用光互連的技術(shù)可突破電互連在帶寬、功耗等方面的瓶頸。本論文對面向片上光互連的高速光子集成芯片做了一些研究。首先,在無源器件方面,針對硅基陣列波導(dǎo)光柵(AWG),提出了三種用于提高集成度、減小器件尺寸的方法。第一種是基于微彎結(jié)構(gòu)的硅基AWG。在AWG的陣列波導(dǎo)區(qū)域設(shè)計一系列周期性的彎曲結(jié)構(gòu),其彎曲半徑5μμm,該彎曲結(jié)構(gòu)可以使AWG在有限的空間實現(xiàn)較大的長度差。研制了一個15通道400 GHz的微彎型AWG,陣列波導(dǎo)區(qū)域由34條帶有微彎結(jié)構(gòu)的波導(dǎo)排列而成,采用交疊型的自由傳輸區(qū)(FPR)結(jié)構(gòu),該器件的總面積只有163μm×147μm。第二種是采用光子晶體作為反射鏡的AWG,它在1450 nm到1650 nm的波長范圍內(nèi),反射率均大于90%。制作的9通道400 GHz光子晶體反射式AWG尺寸僅為134μm×125μm。第三種是采用布拉格光柵作為反射鏡的AWG,光柵的周期370 nm,gap為150 nm,共有10個周期,反射率在300nm的寬帶范圍內(nèi)均大于95%。9通道400GHz的布拉格光柵反射式AWG其尺寸為130μm×100μm。其次,在有源器件方面,設(shè)計并制作了集總電極型的Ⅲ-Ⅴ/Si混合集成電吸收調(diào)制器(EAM),其調(diào)制長度為100 μm,采用兩段式倏逝波耦合的超短taper,該taper總的長度只有45μm,耦合效率大于98%。摸索出了一套基于聚合物BCB輔助鍵合技術(shù)的Ⅲ-Ⅴ/Si混合集成有源器件的制作工藝。然后構(gòu)建測試平臺進行測試,測得其帶寬為17 GHz,并可以觀察到10 Gb/s,20 Gb/s,30 Gb/s效果良好的背靠背傳輸?shù)难蹐D。此外,還可以施加足夠的反向偏置電壓將其作為探測器使用,測得響應(yīng)率為0.72 A/W。再次,在片上光互連集成芯片的探究方面,將無源的AWG和有源的EAM混合集成,研制出5個通道、通道間隔200 GHz、每通道速率不小于20 Gb/s,總?cè)萘繛?00 Gb/s的混合集成調(diào)制器陣列。最后,通過進一步優(yōu)化,實現(xiàn)了180 Gb/s高速混合集成電吸收調(diào)制器陣列、180Gb/s高速混合集成電吸收探測器陣列的研制。并且,在實驗室構(gòu)建了高速片上光互連系統(tǒng),即讓光經(jīng)過調(diào)制器調(diào)制后通過復(fù)用器與解復(fù)用器在終端探測器進行探測,得到了初步研究結(jié)果。
[Abstract]:With the development of information and communication technology, people put forward higher requirements for communication network transmission, high performance computers and high-end servers.Due to its advantages of small size, low energy consumption and large bandwidth, optical integration technology has been more and more popular in optical interconnection, optical communication and other fields.Driven by the desire to reduce costs and improve performance, integrated optoelectronic devices are moving towards higher levels of integration.On the one hand, the silicon waveguide with high refractive index difference is used to reduce the size; on the other hand, all optical functions are integrated into silicon based materials in a monolithic or hybrid manner.Silicon based photonic integrated circuits not only have the advantages of ultra-high bandwidth, ultra-fast transmission rate, anti-electromagnetic interference and low energy consumption, but also compatible with CMOS process, which makes ultra-compact photonic integration system possible.Among chips, optical interconnection can break through the bottleneck of bandwidth and power consumption.In this paper, we do some research on high-speed photonic integrated chip for optical interconnection on chip.Firstly, in the aspect of passive devices, three methods are proposed to improve the integration and reduce the device size for the silicon arrayed waveguide grating (AWGG).The first is silicon based AWGs based on microbending structure.A series of periodic bending structures with a bending radius of 5 渭 m are designed in the arrayed waveguide region of AWG. The bending structure enables the AWG to achieve a large length difference in a limited space.A microcurved AWGs with 15 channels of 400 GHz has been developed. The arrayed waveguide region is composed of 34 waveguides with microcurved structures, and an overlapping free transmission region (FPR) structure is adopted. The total area of the device is only 163 渭 m 脳 147 渭 m.The second is the photonic crystal as the mirror AWG.The reflectivity is greater than 90 in the wavelength range of 1450 nm to 1650 nm.The reflective AWG size of the 9 channel 400 GHz photonic crystal is only 134 渭 m 脳 125 渭 m.The third one is the Bragg grating as the mirror. The grating has a period of 370 nm gap of 150 nm and a total of 10 periods. The reflectivity of the grating is larger than 95.9 channel 400GHz in the wide band range of 300nm. Its size is 130 渭 m 脳 100 渭 m.Secondly, in the aspect of active devices, we design and fabricate the type 鈪,

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