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  本文選題：鎖相環(huán)　切入點(diǎn)：分?jǐn)?shù)分頻頻率綜合器　出處：《西安電子科技大學(xué)》2016年博士論文

【摘要】：鎖相環(huán)頻率綜合器是無線通信系統(tǒng)中的關(guān)鍵模塊,其具有輸出信號頻譜純凈、功耗低、實(shí)現(xiàn)和應(yīng)用成本低等特點(diǎn),因此被廣泛應(yīng)用在射頻前端無線收發(fā)機(jī)中為發(fā)射端基帶信號上變頻或接收端射頻信號下變頻提供本振信號。此外,無線收發(fā)機(jī)中的通信信道選擇也是由頻率綜合器來完成的。隨著當(dāng)前無線通信的快速發(fā)展和智能便攜終端的廣泛普及,采用先進(jìn)CMOS工藝制造的全集成收發(fā)機(jī)SOC已經(jīng)成為低成本無線設(shè)備的主流選擇,并且正在向更低的功耗,更高的集成度、更多的通信模式和功能方向不斷邁進(jìn)。因此必須設(shè)計具有寬輸出頻率范圍的低功耗、低相位噪聲鎖相環(huán)頻率綜合器來適應(yīng)以上的趨勢。本文圍繞低電壓鎖相環(huán)頻率綜合器設(shè)計所面對的挑戰(zhàn)展開,著重對其中關(guān)鍵模塊的電路設(shè)計進(jìn)行了研究。本文的主要工作包含以下幾個方面:首先研究了鎖相環(huán)頻率綜合器的系統(tǒng)設(shè)計方法,通過建立鎖相環(huán)的S域線性時不變(LTI)系統(tǒng)模型來分析和研究環(huán)路的動態(tài)特性和穩(wěn)定性,并且以之為指導(dǎo)來設(shè)計高階環(huán)路濾波器。此外,通過推導(dǎo)環(huán)路內(nèi)部各模塊噪聲轉(zhuǎn)換為相位噪聲的傳遞函數(shù),得到了整數(shù)分頻和分?jǐn)?shù)分頻鎖相環(huán)的相位噪聲分析模型,運(yùn)用此模型可以在系統(tǒng)頂層設(shè)計時就對相位噪聲進(jìn)行優(yōu)化。低電壓條件下傳統(tǒng)B類VCO的性能會發(fā)生嚴(yán)重退化,而在理論上更適合低電壓應(yīng)用的C類VCO卻存在可靠性差、振幅和相位噪聲對PVT變化和頻率調(diào)諧過程敏感等問題。為了解決這些問題,本文提出了一種新的C類VCO結(jié)構(gòu),包含兩個控制環(huán)路。一個低頻共模信號反饋環(huán)路用于將交叉耦合對晶體管偏置在C類工作模式,另一個振幅信號反饋環(huán)路用于控制振幅并使之穩(wěn)定。得益于創(chuàng)新的雙反饋環(huán)路設(shè)計,本文提出的VCO能在起振時產(chǎn)生時變的諧振腔偏置電流,從而具有與傳統(tǒng)B類VCO相似的啟動過程,在可靠性方面獲得了顯著的提升。此外,該新型VCO還具備振幅調(diào)節(jié)功能,能在實(shí)際應(yīng)用根據(jù)特定需求來設(shè)置最佳工作點(diǎn),實(shí)現(xiàn)功耗和相位噪聲指標(biāo)的優(yōu)化。為了驗(yàn)證新VCO結(jié)構(gòu)的有效性,本文采用0.18μm CMOS工藝設(shè)計并實(shí)現(xiàn)了一款雙環(huán)反饋C類VCO原型芯片。測試結(jié)果顯示:該原型VCO的頻率調(diào)諧范圍為4.55-5.16GHz,在1.5V電源電壓下芯片功耗為2.78mW。當(dāng)工作在5GHz振蕩頻率時,距離載波頻率1MHz頻率偏移處的相位噪聲是-123.3dBc/Hz,對應(yīng)得到的FOM值為-192.8dBc/Hz。本文針對低電壓應(yīng)用提出了一種輸出電流可編程高性能電荷泵。該電荷泵由兩個子電荷泵組成,其中每個子電荷泵利用反饋控制和復(fù)制偏置技術(shù)來保證各自的輸出電流具有精確的匹配性。在寬輸出電壓范圍內(nèi),這兩個子電荷泵的輸出電流被設(shè)計成具有相反的變化趨勢,因此利用電流求和結(jié)構(gòu)就能使兩者的變化相互補(bǔ)償,從而得到恒定的總輸出電流。該電荷泵采用0.13μm CMOS工藝設(shè)計,能編程輸出50μA到1.55mA的電流,并以50μA為調(diào)節(jié)步進(jìn)。在1.2V電源電壓下,輸出電壓從0.1V變化到1.05V時,后仿結(jié)果顯示該電荷泵輸出總電流的失配率和變化率不超過0.15%和5%。近乎理想的電流匹配特性能將參考雜散減小到盡可能低的水平,同時還能將電荷泵引起的環(huán)路非線性降到最低,而良好的輸出電流穩(wěn)定性則有助于環(huán)路帶寬保持恒定。關(guān)于頻率綜合器中其他關(guān)鍵模塊的研究,例如鑒頻鑒相器、數(shù)字ΔΣ調(diào)制器、可編程分頻器、雙模預(yù)分頻器等,在本文的相關(guān)章節(jié)做了詳細(xì)討論。最后,采用0.13μm CMOS工藝設(shè)計并實(shí)現(xiàn)了一款分?jǐn)?shù)分頻鎖相環(huán)頻率綜合器原型芯片,面積為1.68mm2。其中VCO采用本文提出的新型結(jié)構(gòu),頻率調(diào)諧范圍是4.4-5.4GHz。頻率綜合器輸出的正交I/Q信號是VCO輸出信號的二分頻結(jié)果,能覆蓋2.2GHz到2.7GHz的頻率范圍。該鎖相環(huán)頻率綜合器采用MASH1-1-1結(jié)構(gòu)的數(shù)字ΔΣ調(diào)制器來實(shí)現(xiàn)分?jǐn)?shù)分頻功能。測試結(jié)果顯示:在1.2V的電源電壓下,頻率綜合器原型芯片的總功耗為12.5mW,在要求的輸出頻率范圍內(nèi),距離載波1MHz頻率偏移處的相位噪聲不超過-122dBc/Hz,而且參考雜散和分?jǐn)?shù)雜散均未超過-70dBc。
[Abstract]:The PLL frequency synthesizer is the key module in wireless communication system, its output signal spectrum purity, low power consumption, realization and application of low cost, so it is widely used of baseband signal frequency or receiving RF signal conversion for local oscillator signal in the RF front-end of wireless transceiver. In addition, the communication channel select the wireless transceiver is accomplished by frequency synthesizer. With the popularization of the rapid development of wireless communication and intelligent mobile terminal, using advanced manufacturing technology to complete CMOS transceiver SOC has become the mainstream of low cost wireless equipment selection, and is to lower power consumption, higher integration, communication mode the function and direction of more forward. So it must be low power design with a wide range of output frequency, low phase noise PLL frequency synthesizer to adapt to The trend. This paper focuses on the design of low voltage phase locked loop frequency synthesizer challenge, focuses on the circuit design of the key modules were studied. The main work of this paper includes the following aspects: firstly, research the system design method of PLL frequency synthesizer, unchanged through the S domain established a linear phase locked loop when (LTI) system model to analyze and study the loop dynamics and stability, and in order to guide the design of high order loop filter. In addition, through the derivation of each module within the loop noise transfer function for phase noise, the phase noise of the integer frequency and fractional PLL analysis model, using this model in the top-level design is to optimize the phase noise. The traditional class B under the condition of low voltage VCO performance will be degraded seriously, and in theory should be more suitable for low voltage The C class VCO has poor reliability, the amplitude and phase noise on the PVT change and frequency tuning process sensitive. In order to solve these problems, this paper proposes a new C VCO structure contains two control loop. A low frequency common mode signal feedback loop for cross coupled transistor bias in C type of work mode, another feedback loop is used to control the amplitude of signal amplitude and make it stable. Thanks to the innovative design of double feedback loop, the proposed VCO can generate time-varying bias current of resonant cavity in vibration, and thus has the traditional class B VCO boot process similar to that obtained significant improvement the reliability of the model. In addition, VCO also has amplitude adjustment function, can be set according to the specific needs of the best work in the practical application, realize the optimization of power and phase noise index. In order to verify the validity of the new VCO structure, This paper uses 0.18 m CMOS process to design and realize a double loop feedback class C VCO prototype. The test results show that the frequency tuning range of the prototype of VCO is 4.55-5.16GHz, the supply voltage of 1.5V chip power consumption is 2.78mW. when operating in the 5GHz oscillation frequency, the phase noise at the carrier frequency 1MHz frequency offset distance is -123.3dBc/Hz corresponding, the FOM value obtained for -192.8dBc/Hz. based on Low Voltage Applications presents a high performance programmable current charge pump. The charge pump consists of two charge pump, wherein each sub charge pump using feedback control and replication bias technology to ensure the output current with their matching accuracy. In the wide output voltage within the range of the output current of the two sub charge pump is designed to have the opposite trend, the current and the structure can make the change from mutual compensation The total output current is constant. 0.13 m CMOS process is adopted in the design of the charge pump can output current programming 50 A to 1.55mA, and 50 A for adjusting step. Under the 1.2V supply voltage, the output voltage changes from 0.1V to 1.05V, simulation results show that the charge pump output the current mismatch rate and the rate of change is less than 0.15% 5%. and the current nearly ideal matching characteristics can be reduced to the reference spur as low as possible, but also will cause the nonlinear loop charge pump to a minimum, while the output current stability is helpful to maintain constant loop bandwidth on the other. The key module in the frequency synthesizer, such as PFD, digital modulator, programmable divider, prescaler, discussed in detail in the paper. Finally, using 0.13 m CMOS technology to design and realize a fraction Frequency PLL frequency synthesizer prototype chip, new structure area of 1.68mm2. where VCO is proposed, the frequency tuning range is I/Q 4.4-5.4GHz. orthogonal frequency synthesizer output signal is the output signal of VCO two frequency, frequency range can cover the 2.2GHz to 2.7GHz. The PLL frequency synthesizer using digital delta sigma modulator MASH1-1-1 the structure to achieve the fractional frequency function. The results showed that: in the power supply voltage of 1.2V, the total power consumption of the frequency synthesizer prototype chip is 12.5mW, the output in the specified frequency range, phase noise of carrier frequency distance 1MHz offset is less than -122dBc/Hz, and the reference spur and fractional spurs did not exceed -70dBc.

【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2016
【分類號】：TN74

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