本文關(guān)鍵詞：集成電路新型ESD防護(hù)器件研究　出處：《浙江大學(xué)》2016年博士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 集成電路 ESD防護(hù)器件設(shè)計(jì) GGISCR器件 組件級(jí)ESD防護(hù) 系統(tǒng)級(jí)ESD防護(hù)

【摘要】：集成電路的ESD (Electrostatic Discharge)防護(hù)設(shè)計(jì)是提高集成電路和電子系統(tǒng)可靠性的重要關(guān)鍵技術(shù)。本文分析了集成電路ESD防護(hù)設(shè)計(jì)及其應(yīng)用背景,提出了新穎的ESD防護(hù)器件,滿足了應(yīng)用領(lǐng)域新技術(shù)的要求,并借助理論分析和TCAD (Technology Computer Aided Design)仿真設(shè)計(jì)研究了器件的工作機(jī)理,對(duì)有關(guān)結(jié)果進(jìn)行流片實(shí)驗(yàn)和測(cè)試驗(yàn)證。具體研究?jī)?nèi)容和創(chuàng)新點(diǎn)如下：1.提出了基于0.35μm CMOS工藝的新型GGISCR (Gate-Grounded-nMOS Incorporated Silicon Controlled Rectifier)器件,相比目前通用的LVTSCR (Low Voltage Triggered Silicon Controlled Rectifier)器件,在不增加器件面積、不降低器件魯棒性的前提下可將維持電壓提升到7.9V,40μm寬度的GGISCR器件的失效電流達(dá)到4.4A,解決了傳統(tǒng)ESD防護(hù)器件在器件面積、魯棒性和維持電壓三者之間折中矛盾的關(guān)鍵難題。論文借助使用TCAD仿真工具,研究了器件在ESD應(yīng)力下的直觀重要物理量,包括：電場(chǎng)、電流密度和碰撞離化率等,結(jié)合上述結(jié)果對(duì)其工作機(jī)制進(jìn)行分析和闡述。有關(guān)結(jié)果發(fā)表在TED期刊,并申請(qǐng)發(fā)明專利。2.提出了基于0.35μm 40V BCD (Bipolar CMOS DMOS)工藝的改進(jìn)型GGISCR器件,通過優(yōu)化器件結(jié)構(gòu)和并聯(lián)小尺寸GGLDMOS (gate-grounded Lateral Double-diffused MOS)器件,完整地驗(yàn)證了其ESD防護(hù)的有效性,該設(shè)計(jì)成功應(yīng)用于某上市公司的電源管理芯片的電源鉗位單元。主要的創(chuàng)新點(diǎn)是基于BCD工藝的特點(diǎn)進(jìn)一步縮小了器件的回滯窗口,失效電流達(dá)到3.5A。通過堆疊的方式極大地提高了器件的維持電壓,解決了電源鉗位單元存在的閂鎖問題,滿足18V和24V電源應(yīng)用,技術(shù)指標(biāo)優(yōu)越。3.設(shè)計(jì)了一種新型ESD防護(hù)器件FP-LDMOS-SCR (Floating P+Lateral Double-diffused MOS Silicon Controlled Rectifier)器件,用于0.35μm 40V BCD工藝I/O接口的ESD防護(hù)。通過在LDMOS器件漏端設(shè)計(jì)浮空P+區(qū),將器件的失效電流提升到2.7A,且不影響器件正常工作的I-V特性。FP-LDMOS-SCR器件提升了高壓I/O接口的ESD魯棒性且降低了閂鎖風(fēng)險(xiǎn)。有關(guān)結(jié)果發(fā)表在MR期刊。4.在0.35μm 80V BCD工藝平臺(tái)上設(shè)計(jì)了LDMOS-SCR器件,解決了傳統(tǒng)LDMOS器件在ESD應(yīng)力下出現(xiàn)過早失效的關(guān)鍵難題。TLP測(cè)得LDMOS-SCR器件失效電流值為4.3A。通過在漏端插入一個(gè)場(chǎng)氧結(jié)構(gòu),將LDMOS-SCR器件的擊穿電壓從92V提升到99V,進(jìn)一步增強(qiáng)了器件耐壓特性。5.設(shè)計(jì)了具有超高魯棒性的ESD防護(hù)器件,其失效電流高達(dá)18.9A,滿足IEC61000-4-2 15KV接觸放電的ESD防護(hù)等級(jí)。主要的創(chuàng)新點(diǎn)是在對(duì)GGISCR器件的失效機(jī)理分析的基礎(chǔ)上,設(shè)計(jì)了高效的圓形版圖器件,其FOM(Figure of Merit)值為137AV/pF,比常規(guī)的多指條型版圖性能提升73%,技術(shù)指標(biāo)遠(yuǎn)優(yōu)于目前業(yè)界的主流產(chǎn)品,有關(guān)結(jié)果已申請(qǐng)發(fā)明專利。6.設(shè)計(jì)了一種新型的穿通型五層N++P+PP+N++結(jié)構(gòu)的TVS (Transient Voltage Suppressor)器件。其十二指條型器件獲得超過10A的失效電流,不大于0.17pF的寄生電容,解決了傳統(tǒng)TVS器件寄生電容過大影響系統(tǒng)信號(hào)完整性的問題,滿足諸如USB3.0和HDMI1.4高速接口的系統(tǒng)級(jí)ESD防護(hù)應(yīng)用,技術(shù)指標(biāo)遠(yuǎn)優(yōu)于目前業(yè)界的主流產(chǎn)品。有關(guān)結(jié)果投稿IEEJ期刊(已錄用),并申請(qǐng)發(fā)明專利。
[Abstract]:Integrated circuit ESD (Electrostatic Discharge) is a key technique to improve protection design reliability of integrated circuit and electronic system. This paper analyzes the design of integrated circuit ESD protection and its application background, put forward the ESD protection device novel, meet new application technical requirements, and by means of theoretical analysis and TCAD (Technology Computer Aided Design) simulation design studies the working mechanism of the device, carried out experiments and tests to verify the results. The specific contents are as follows: 1. novel GGISCR 0.35 m based on CMOS Technology (Gate-Grounded-nMOS Incorporated Silicon Controlled Rectifier) device, compared to the current general LVTSCR (Low Voltage Triggered Silicon Controlled Rectifier) device. Without increasing device area, robustness under the premise of the device will maintain the voltage up to 7. is not reduced 9V, the failure of current GGISCR device 40 m width up to 4.4A, to solve the traditional ESD protection devices in the device area, the key problem of compromise the contradiction between robustness and maintain the voltage of three. With the use of TCAD simulation tools, on the device under stress directly important physical quantities in ESD include: electric field. The current density and the impact ionization rate, combined with the results of its work mechanism is described and analyzed. The results were published in the Journal TED, the invention patent.2. proposed 0.35 m 40V based on BCD (Bipolar CMOS DMOS) and the application of improved GGISCR device technology, through the optimization of device structure and parallel small size GGLDMOS (gate-grounded Lateral Double-diffused MOS devices), to validate the effectiveness of ESD protection, the power management chip design is successfully applied to a listed company in the power clamp unit. The main innovations are based The characteristics of BCD technology in further reducing the device hysteresis window, failure current reaches 3.5A. by stacking method greatly improves the device to maintain the voltage, solve the existing power clamp unit latch, meet the requirements of 18V and 24V power applications, technical superiority index.3. design of a new type of ESD protection device FP-LDMOS-SCR (Floating P+Lateral Double-diffused MOS Silicon Controlled Rectifier) devices, ESD protection for 0.35 m 40V BCD process I/O interface. Through the design of floating drain area of P+ on the LDMOS device, the device failure current up to 2.7A, the I-V characteristics of.FP-LDMOS-SCR devices and does not affect the normal working of the device to enhance the robustness of ESD high voltage I/O interface and reduce the latch risk. Relevant results published in the MR Journal.4. 0.35 m 80V BCD technology platform is designed to solve the traditional LDMOS-SCR devices, LDMOS devices in ESD Under the.TLP key problem of premature failure of the measured current value of 4.3A. LDMOS-SCR device failure through the drain into a field oxide structure, the breakdown voltage of LDMOS-SCR devices increased from 92V to 99V, to further enhance the breakdown voltage characteristics of.5. design with ESD protection device of high robustness, high current failure up to 18.9A, to meet the ESD protection grade IEC61000-4-2 15KV contact discharge. The main innovation is the basis of analysis on the failure mechanism of GGISCR devices on the design of the circular layout device with high efficiency, the FOM (Figure of Merit) is 137AV/ pF, a 73% more than the conventional lifting type layout performance, technical index is far better than the current mainstream products in the industry, the relevant results have been applied to a new five layer through the N++P+PP+N++ structure of TVS.6. (Transient Voltage design patent Suppressor). The twelve refers to the device type A failure current is more than 10A, not more than the parasitic capacitance of 0.17pF, to solve the traditional TVS devices too large parasitic capacitance effect system of signal integrity, meet system level ESD protection applications such as USB3.0 and HDMI1.4 high speed interface, technical index is far better than the current mainstream industry products. The results contribute IEEJ Journal (accepted), and apply for a patent.

【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN40

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