本文關(guān)鍵詞：基于逐次逼近結(jié)構(gòu)的高速低功耗模數(shù)轉(zhuǎn)換器研究　出處：《東南大學(xué)》2017年博士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 模數(shù)轉(zhuǎn)換器 逐次逼近 數(shù)模轉(zhuǎn)換器 電容陣列 比較器 邏輯控制 冗余補(bǔ)償 電容失配校正 失調(diào)校正 雙電容陣列

【摘要】：隨著無(wú)線通信、便攜式測(cè)試儀器等方面的快速發(fā)展,要求模數(shù)轉(zhuǎn)換器(ADC)的速度越來(lái)越高、功耗越來(lái)越低。逐次逼近型(SAR)ADC擁有固有的結(jié)構(gòu)簡(jiǎn)單、面積小、功耗低等特性,工藝特征尺寸的不斷降低使得SAR ADC具有了實(shí)現(xiàn)高速轉(zhuǎn)換的可能性,而移動(dòng)通信、物聯(lián)網(wǎng)、消費(fèi)電子的飛速發(fā)展,對(duì)高速低功耗ADC也提出了很大的需求。所以研究以逐次逼近結(jié)構(gòu)為基礎(chǔ)的高速低功耗ADC對(duì)高速低功耗的應(yīng)用領(lǐng)域具有非常重要的意義。本課題對(duì)單核SAR ADC的設(shè)計(jì)進(jìn)行了深入的研究,對(duì)進(jìn)一步降低SAR ADC的功耗和提高SAR ADC轉(zhuǎn)換速度的關(guān)鍵技術(shù)進(jìn)行了探討。本文研究的主要內(nèi)容如下:1、本文對(duì)SAR ADC中低功耗DAC開關(guān)電容陣列進(jìn)行了深入研究,提出了一種低功耗的基于Vcm的分離電容陣列結(jié)構(gòu)。該結(jié)構(gòu)通過(guò)將最高位電容分離為1組二進(jìn)制權(quán)重的電容陣列,以及采用終端匹配電容與Vcm相結(jié)合產(chǎn)生最低位量化所需的參考電壓的技術(shù),減少了 DAC電容陣列所需的單位電容個(gè)數(shù)和平均充放電功耗,提高了 DAC的速度。和傳統(tǒng)的結(jié)構(gòu)相比,基于Vcm的分離電容陣列結(jié)構(gòu)所需的單位電容個(gè)數(shù)減少了 75%,功耗降低了 93.7%,建立速度提高了 25%,同時(shí)還使得DAC輸出共模電平基本保持不變,減小了比較器輸入端的動(dòng)態(tài)失調(diào)。采用所提出的基于Vcm的分離電容陣列結(jié)構(gòu),在90nm CMOS工藝下設(shè)計(jì)了 10位SAR ADC,并對(duì)其中的邏輯控制電路模塊進(jìn)行了優(yōu)化設(shè)計(jì),縮短了邏輯控制電路的延遲,提高了 SAR ADC的轉(zhuǎn)換速度。仿真結(jié)果表明,該ADC采樣速率可達(dá)150MS/s,有效位數(shù)為9.9位,功耗為2.2mW。2、為了進(jìn)一步提高SAR ADC的轉(zhuǎn)換速度,本文對(duì)DAC模塊的速度優(yōu)化技術(shù)進(jìn)行了研究。分析和討論了采用冗余補(bǔ)償技術(shù)縮短DAC建立時(shí)間的方法,提出了一種基于二進(jìn)制冗余補(bǔ)償及分離電容技術(shù)的分段結(jié)構(gòu)DAC。通過(guò)二進(jìn)制冗余補(bǔ)償技術(shù),降低了 DAC建立精度的需求,縮短了 DAC的建立時(shí)間;通過(guò)分離電容技術(shù)減小了 DAC建立時(shí)間常數(shù),提高了 DAC的建立速度。在12位SAR ADC中,與傳統(tǒng)分段結(jié)構(gòu)DAC相比,提出的DAC的總的建立時(shí)間減少了 55%,速度提高了 1倍�；谔岢龅母咚貲AC結(jié)構(gòu),在0.18μm CMOS工藝下實(shí)現(xiàn)了一款12位高速SAR ADC。測(cè)試結(jié)果表明,該ADC的最高轉(zhuǎn)換速率可達(dá) 100MS/s,SNDR 為 59dB,功耗為 6.2mW。3、針對(duì)SAR ADC中DAC電容陣列的電容失配導(dǎo)致的非線性問題,本文研究了 DAC電容陣列中電容失配的校正技術(shù),提出了一種基于低位電容陣列復(fù)用的數(shù)字域自校正技術(shù)。該技術(shù)通過(guò)復(fù)用低位段電容陣列作為校正DAC,在ADC開始正常轉(zhuǎn)換之前,對(duì)高位段電容陣列電容從高到低逐位的進(jìn)行失配誤差檢測(cè)和量化,并將誤差碼存儲(chǔ)起來(lái)。正常轉(zhuǎn)換開始后,將輸出的原始碼與誤差碼求和獲得最終的輸出。為了解決失配誤差估計(jì)過(guò)程中所需要的比較器的失調(diào)電壓校正,本文對(duì)在兩級(jí)動(dòng)態(tài)比較器的第一級(jí)和第二級(jí)分別引入額外的負(fù)載不平衡電容補(bǔ)償失調(diào)電壓的方法進(jìn)行了對(duì)比分析,發(fā)現(xiàn)在第一級(jí)實(shí)現(xiàn)失調(diào)電壓補(bǔ)償?shù)姆椒ǜ袃?yōu)勢(shì)。利用這一分析結(jié)果,提出了一種基于負(fù)載電容補(bǔ)償?shù)氖д{(diào)校正電路,使得比較器的失調(diào)電壓減小到1LSB以內(nèi),滿足了系統(tǒng)的精度要求�；谔岢龅臄�(shù)字域自校正技術(shù)設(shè)計(jì)了一款12位SARADC,并在40nm CMOS工藝下進(jìn)行了電路級(jí)仿真。仿真結(jié)果表明,提出的數(shù)字域自校正技術(shù)有效的減小了電容失配對(duì)SAR ADC性能的影響。4、本文對(duì)低功耗的雙電容陣列DAC進(jìn)行了研究,提出了改進(jìn)型雙電容陣列DAC。與傳統(tǒng)結(jié)構(gòu)相比,改進(jìn)后的雙電容陣列DAC在功耗和面積上分別減少了 99.3%和71.9%。本文還對(duì)兩級(jí)動(dòng)態(tài)比較器結(jié)構(gòu)進(jìn)行了研究,提出了改進(jìn)的兩級(jí)動(dòng)態(tài)比較器結(jié)構(gòu),通過(guò)增加鎖存器作為第一級(jí)的負(fù)載,提高比較器的增益,從而進(jìn)一步提高比較器的速度。
[Abstract]:With the rapid development of wireless communication, portable instrument and other aspects of the requirements of analog-to-digital converter (ADC) has become more and more high, more and more low power consumption. The successive approximation (SAR) ADC has inherent structure simple, small size, low power consumption characteristics, to reduce the feature size of the SAR ADC has the possibility of achieving high speed conversion, and mobile communications, networking, rapid development of consumer electronics, a great demand for high speed and low power ADC is proposed. So the research to the successive approximation applications of high speed low power ADC structure based on high speed and low power consumption has very important significance. The design of the single core SAR ADC this topic conducted in-depth research, to further reduce the power consumption of SAR ADC and discusses the key technology to improve the SAR ADC conversion rate. The main contents of this paper are as follows: 1, the SAR ADC low power DAC Close the capacitor array is studied, proposes a low power isolation capacitor array structure based on Vcm. The structure by high capacitance capacitor array is separated into 1 groups of binary weights, and the use of terminal matching capacitor combined with Vcm to generate the reference voltage required for quantification of low technology, reduced by DAC capacitor array required unit capacitor number and average charge and discharge power, improve the speed of DAC. Compared with the traditional structure, the number of unit capacitors separating capacitor array structure of Vcm based on the desired reduced by 75%, power consumption is reduced by 93.7%, a rate increased by 25%, while also making the DAC output common mode level of basic remain unchanged, reduce the input of the dynamic comparator disorders. By separating the capacitor array structure based on Vcm proposed by 90nm CMOS in the process design of 10 SAR ADC, and the control logic The circuit module is optimized, the logic control circuit to shorten the delay, improve the SAR ADC conversion speed. The simulation results show that the ADC sampling rate up to 150MS/s, 9.9 effective digits, power consumption is 2.2mW.2, in order to further improve the SAR ADC conversion speed, the speed of DAC module on the optimization technology study. Analyzed and discussed using redundancy compensation technology to shorten the time of establishing the DAC method, the paper proposes a segmentation structure of DAC. binary redundancy compensation and capacitor separation technology based on binary through redundancy compensation technology, reduces the DAC requirement, shorten the DAC setup time; by separating the capacitor technology reduces the DAC time constant to improve the speed of DAC, was established. In 12 SAR ADC, and the traditional segmental structure compared to DAC, DAC proposed the total build time reduced by 55%, speed 1 times higher. High speed DAC structure based on 0.18 m CMOS technology to achieve a 12 bit high speed SAR ADC. test results show that the highest conversion rate of up to 100MS/s ADC, SNDR 59dB, power consumption of 6.2mW.3, aiming at the nonlinear capacitance of DAC capacitor array SAR in ADC due to the mismatch problem is studied in this paper. The capacitor mismatch correction DAC capacitor array, this paper presents a self calibration technique of digital domain multiplexing based on low capacitance array. The technique by multiplexing the low section capacitor array as the calibration DAC, before the start of the normal conversion in ADC, the peak of capacitor array capacitance from high to low by a mismatch error detection and quantization, and error code stored. Normal conversion after the start of the original code output and error codes and obtain the final output. In order to solve the mismatch error estimation of offset comparator needed in Piezoelectric The correction in the two stage dynamic comparator is the first level and second level respectively introduce additional load balancing method of capacitance compensation offset voltage was analyzed, found in the first level implementation advantage offset voltage compensation method. The results of this analysis, propose an offset correction circuit load capacitance compensation based on the offset voltage of the comparator is reduced to less than 1LSB, to meet the requirements of the accuracy of the system. Design of a 12 bit SARADC digital domain is proposed based on self correction, and the circuit level simulation in 40nm CMOS process. The simulation results show that the proposed digital self-tuning technology effectively reduces the influence of the.4 capacitor mismatch on the performance of ADC SAR, the DAC of low power dual capacitor array is studied, put forward the improved double capacitor array DAC. compared with the traditional structure, the improved double capacitor array Column DAC in power and area were reduced by 99.3% and 71.9%. the two level dynamic comparator structure was studied, this paper proposes two level dynamic comparator with improved structure, by increasing the latch as the first level load, improve the comparator gain, so as to further improve the speed of the comparator.

【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN792

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