本文關(guān)鍵詞：薄層SOI高壓LDMOS背柵調(diào)制模型與特性研究　出處：《電子科技大學(xué)》2016年博士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 絕緣體上硅 橫向雙擴(kuò)散金屬氧化物半導(dǎo)體 背柵效應(yīng) 熱載流子 負(fù)偏置溫度不穩(wěn)定

【摘要】：SOI(Silicon On Insulator,絕緣體上硅)高壓LDMOS(Lateral Double-diffused Metal Oxide Semicondutor,橫向雙擴(kuò)散金屬氧化物半導(dǎo)體)器件因其低功耗、高頻率、高集成度等特點(diǎn),廣泛用于汽車電子、醫(yī)療電子、智能家電和航空航天等智能功率集成電路。相比厚層SOI結(jié)構(gòu),薄層SOI LDMOS具有良好的工藝兼容性和較少的寄生效應(yīng),在功率集成電路,特別是功率開關(guān)和驅(qū)動(dòng)集成電路中有著良好的應(yīng)用前景。但是由于背柵效應(yīng),薄層SOI LDMOS器件性能和可靠性受到嚴(yán)重影響,尤其是p溝道LDMOS。目前背柵效應(yīng)研究主要集中于對(duì)器件擊穿電壓的影響,對(duì)比導(dǎo)通電阻、甚至可靠性的影響鮮有報(bào)道。負(fù)偏置溫度不穩(wěn)定性(Negative Bias Temperature Instability,簡稱NBTI)是p溝道MOS器件最重要的可靠性問題之一,SOI高壓器件埋氧層長期受到背柵偏置影響,其背柵NBTI效應(yīng)會(huì)對(duì)器件特性產(chǎn)生影響。然而目前NBTI研究主要針對(duì)柵氧化層,對(duì)于SOI器件埋氧層研究未見報(bào)道。本論文圍繞背柵效應(yīng),基于場荷調(diào)制理論,研究了薄層SOI高壓場p溝道LDMOS比導(dǎo)通電阻、擊穿電壓特性和陷阱電荷誘致退化效應(yīng)。提出背柵場調(diào)制耐壓模型,揭示了背柵對(duì)擊穿電壓和比導(dǎo)通電阻影響機(jī)理。體內(nèi)電場受到背柵電壓調(diào)制,引起體內(nèi)電荷分布變化,形成雙導(dǎo)電模式,極大改善了擊穿電壓與比導(dǎo)通電阻關(guān)系。提出陷阱電荷電導(dǎo)調(diào)制模型,揭示了器件背柵NBTI和熱載流子退化機(jī)理。背柵NBTI和熱載流子效應(yīng)產(chǎn)生的場致陷阱電荷引起體內(nèi)電荷分布變化,從而導(dǎo)致器件特性發(fā)生退化。主要?jiǎng)?chuàng)新點(diǎn)如下:1.提出背柵場調(diào)制耐壓模型基于場荷調(diào)制理論,提出背柵場調(diào)制耐壓模型,揭示了薄層SOI高壓場p溝道LDMOS背柵電壓對(duì)擊穿電壓和比導(dǎo)通電阻影響機(jī)理,給出了背柵電壓與表面擊穿電壓、比導(dǎo)通電阻之間關(guān)系。體內(nèi)電場受到背柵電壓調(diào)制,導(dǎo)致表面擊穿電壓與背柵電壓呈線性關(guān)系:BVs=0.98×VBG 198.4。同時(shí)調(diào)制體內(nèi)場引起體內(nèi)電荷分布變化,形成雙導(dǎo)電模式,使得器件比導(dǎo)通電阻Ron,sp取決于漂移導(dǎo)電層和積累導(dǎo)電層并聯(lián)的結(jié)果:Ron,sp=1/(1.45×10-13 ts ND 7.07×10-4 VBG),極大地改善了擊穿電壓與比導(dǎo)通電阻的關(guān)系。2.提出背柵穿通判據(jù)和器件耐壓設(shè)計(jì)準(zhǔn)則提出背柵穿通判據(jù),揭示器件背柵穿通機(jī)理,可適用于所有SOI p溝道LDMOS器件。提出SOI高壓場p溝道LDMOS器件耐壓設(shè)計(jì)準(zhǔn)則,即電源電壓VHV|BVs(VBG=VHV)|,|BVb|和|BVp|,同時(shí)考慮了漏極電壓與背柵電壓。實(shí)驗(yàn)結(jié)果顯示,器件擊穿電壓達(dá)到-366 V,比導(dǎo)通電阻僅為6.6Ω?mm2�；谘芯拷Y(jié)果,首創(chuàng)目前國際集成場p LDMOS的最薄導(dǎo)電硅層系列SOI高低壓兼容工藝,并在國防裝備得到應(yīng)用,取得良好的社會(huì)和經(jīng)濟(jì)效益。3.提出薄層SOI高壓場p溝道LDMOS陷阱電荷電導(dǎo)調(diào)制模型提出陷阱電荷電導(dǎo)調(diào)制模型,揭示了薄層SOI高壓場p溝道LDMOS背柵NBTI和熱載流子引起線性電流退化的機(jī)理。背柵NBTI和熱載流子效應(yīng)的場致陷阱電荷引起漂移區(qū)和溝道電荷發(fā)生變化,從而導(dǎo)致線性電流退化。背柵NBTI在埋氧層產(chǎn)生總正的場致陷阱電荷,降低體內(nèi)積累層電荷密度、擊穿點(diǎn)處電場峰值和能帶,導(dǎo)致線性電流降低、擊穿電壓和靜態(tài)電流增加。兩種相反的熱載流子效應(yīng)機(jī)理共同決定了線性電流退化:溝道區(qū)里的熱空穴注入產(chǎn)生正的陷阱電荷,導(dǎo)致閾值增加,線性電流降低;漂移區(qū)柵極場板末端的熱電子注入產(chǎn)生負(fù)的陷阱電荷,導(dǎo)致線性電流增加。
[Abstract]:SOI (Silicon On Insulator, silicon on insulator) high voltage LDMOS (Lateral Double-diffused Metal Oxide Semicondutor, lateral double diffused metal oxide semiconductor) devices due to its low power consumption, high frequency, high integration and so on, are widely used in automotive electronics, medical electronics, aerospace and other smart appliances and smart power integrated circuit. Compared with the thick SOI structure, thin layer SOI LDMOS has good process compatibility and less parasitic effect. It has a good application prospect in power integrated circuits, especially in power switches and driving integrated circuits. However, due to the back gate effect, the performance and reliability of thin layer SOI LDMOS devices are seriously affected, especially the P channel LDMOS. At present, the research on the back gate effect is mainly focused on the impact of the breakdown voltage on the device, and there are few reports on the effect of comparing the resistance and even the reliability. Negative Bias Temperature Instability (referred to as NBTI) is one of the most important reliability problems of P channel MOS devices. The oxide layer of SOI high voltage device is influenced by back grid bias for a long time, and its back gate NBTI effect will have an impact on device characteristics. However, at present, the study of NBTI mainly focuses on the gate oxide layer, and there is no report on the study of the embedded oxygen layer of SOI devices. Focusing on the back gate effect, based on the field charge modulation theory, the P channel LDMOS specific conduction resistance, breakdown voltage characteristics and trap induced degradation effect of thin SOI high voltage field are studied. A back gate field modulated pressure resistance model is proposed, and the influence mechanism of the back gate on the breakdown voltage and the specific resistance is revealed. The electric field in the body is modulated by the back gate voltage, which causes the change of the charge distribution in the body and forms a double conduction mode, which greatly improves the relationship between the breakdown voltage and the specific resistance. The trap charge conductance modulation model is proposed, and the mechanism of the back gate NBTI and the thermal carrier degradation is revealed. The field induced charge generated by the back gate NBTI and the hot carrier effect causes the change in the charge distribution in the body, which leads to the degradation of the device characteristics. The main innovations are as follows: 1. put back pressure field modulation model of gate charge modulation based on the theory, put forward the back gate field voltage modulation model, reveals the thin layer SOI high voltage field P channel LDMOS back gate voltage on the breakdown voltage and on resistance mechanism, gives the back gate voltage and breakdown voltage, guide surface the relationship between the resistance. The electric field in the body is modulated by the back gate voltage, which leads to a linear relationship between the surface breakdown voltage and the back grid voltage: BVs=0.98 x VBG 198.4. At the same time in the modulation field caused by changes in the charge distribution, the formation of double conduction mode, which makes the device specific on resistance of Ron SP depends on the conductive layer and the conductive layer drift accumulation in parallel results: Ron, sp=1/ (1.45 x 10-13 TS ND 7.07 * 10-4 VBG), has greatly improved the relationship between breakdown voltage and on resistance the. 2., put forward the criterion of back gate penetration and design criterion of device voltage, and put forward the criterion of back gate penetration. It reveals the mechanism of device's back gate perforating, and it can be applied to all SOI P channel LDMOS devices. The SOI high field P channel LDMOS device voltage design criterion, namely the power supply voltage VHV|BVs (VBG=VHV) |, |BVb| and |BVp|, considering the drain voltage and back gate voltage. The experimental results show that the breakdown voltage of the device reaches -366 V, and the specific resistance is only 6.6 Omega? Mm2. Based on the research results, we first created the thin and conductive silicon series SOI high and low voltage compatible technology of international integrated field P LDMOS, which has been applied in national defense equipment and achieved good social and economic benefits. 3., a thin layer SOI high voltage field P channel LDMOS trap charge conductance modulation model is proposed. The trap charge conductance modulation model is proposed, revealing the mechanism of the linear SOI current degradation of thin SOI high voltage field, P channel LDMOS back gate NBTI and hot carrier. The field induced charge of the back gate NBTI and the hot carrier effect causes the change of the drift area and channel charge, which leads to the degradation of the linear current. In the buried oxygen layer, the total gate positive NBTI generates the total positive field trapped charge, which reduces the accumulation layer charge density, the electric field peak and the energy band at the breakdown point, resulting in the decrease of the linear current, the increase of breakdown voltage and quiescent current. Two opposite the hot carrier effect mechanism determines the linear current degradation: hot hole injection channel in trap charge is generated, leading to increases the threshold current decreases linearly; the drift region gate field plate at the end of the hot electron injection produced negative trap charge, resulting in increased line current.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN386

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