本文選題：數(shù)字三維示波器 + DDR3　； 參考：《電子科技大學(xué)》2016年碩士論文

【摘要】：隨著信號的頻率和復(fù)雜性逐漸增加,更大的存儲深度以及更高的數(shù)據(jù)存取和處理速率是當(dāng)代示波器提高對異常信號捕獲能力的重要手段。作為示波器的主要存儲模塊,DDR3 SDRAM設(shè)計的好壞直接影響到前端的數(shù)據(jù)采集模塊(ADC)和后端的波形處理模塊的工作效率。本課題以數(shù)字三維示波器為硬件設(shè)計平臺,通過DDR3存儲模塊的硬件設(shè)計,實(shí)現(xiàn)了深存儲下的分段錄制與三維映射功能。本課題采用FPGA+DDR3的經(jīng)典存儲架構(gòu),利用DDR3的大容量與高存取速率,使得數(shù)字三維示波器在深存儲模式下依然具有高速的數(shù)據(jù)處理與響應(yīng)能力。論文的主要研究內(nèi)容包括DDR3及其外圍電路的設(shè)計、電源分配網(wǎng)絡(luò)的設(shè)計、信號和電源完整性的設(shè)計、深存儲功能的設(shè)計與實(shí)現(xiàn)等。在DDR3模塊的硬件設(shè)計中,通過MIG核簡化設(shè)計流程,采用4:1的數(shù)據(jù)傳輸模式,使得DDR3存儲模塊的讀寫速度最高可達(dá)6.4GB/s,提高了數(shù)據(jù)的存取效率。在硬件系統(tǒng)設(shè)計方面,通過去耦、隔離、阻抗匹配等各種手段,降低系統(tǒng)噪聲,提高信號和電源完整性,并達(dá)到了國家電磁兼容性要求中的電磁輻射標(biāo)準(zhǔn)(GB4824,頻率:30~1000MHz)。在DDR3的深存儲功能設(shè)計方面,改進(jìn)了以往單一的錄制和映射模塊,通過分段錄制和多幅波形集中映射的方式,不僅減小了死區(qū)時間,還大大提高了數(shù)字三維示波器對異常信號的捕獲能力。除此之外,本課題還重點(diǎn)探究了DDR3存儲模塊設(shè)計中的重難點(diǎn)(高速硬件設(shè)計、深存儲中的關(guān)鍵技術(shù)等),最終完成了數(shù)字三維示波器中DDR3存儲模塊的硬件設(shè)計,實(shí)現(xiàn)了深存儲下的分段錄制、回放和三維映射等功能,以及最大可變存儲深度達(dá)到280Mpts,波形捕獲率超過200,000wfms/s。
[Abstract]:With the increasing of the frequency and complexity of the signal, greater storage depth and higher data access and processing rate are the important means for the modern oscilloscope to improve its ability to capture abnormal signals. As the main storage module of oscilloscope, the design of DDR3 SDRAM directly affects the efficiency of the front-end data acquisition module (ADC) and the back-end waveform processing module. In this paper, the digital 3D oscilloscope is used as the hardware design platform. Through the hardware design of DDR3 storage module, the function of segmented recording and 3D mapping under deep storage is realized. In this paper, the classical storage architecture of FPGA DDR3 is adopted, and the large capacity and high access rate of DDR3 make the digital 3D oscilloscope still have high speed data processing and response ability in deep storage mode. The main contents of this paper include the design of DDR3 and its peripheral circuits, the design of power distribution network, the design of signal and power supply integrity, and the design and implementation of deep storage function. In the hardware design of DDR3 module, the design flow is simplified by MIG core, and the 4:1 data transmission mode is adopted. The reading and writing speed of DDR3 storage module is up to 6.4 GB / s, and the data access efficiency is improved. In the aspect of hardware system design, by means of decoupling, isolation, impedance matching and so on, the noise of the system is reduced, the signal and power integrity are improved, and the electromagnetic radiation standard GB4824 and the frequency of 1: 30 ~ 1000MHz are achieved. In the design of DDR3 deep storage function, the former single recording and mapping module is improved. The dead zone time is not only reduced by segmental recording and multi-waveform centralized mapping, but also by the design of DDR3 deep storage function. It also greatly improves the ability of the digital three-dimensional oscilloscope to capture the abnormal signal. In addition, this subject also focuses on the design of DDR3 storage module, including the high speed hardware design, the key technology of deep storage and so on. Finally, the hardware design of DDR3 storage module in the digital 3D oscilloscope is completed. The functions of segment recording, playback and 3D mapping under deep storage are realized, and the maximum variable storage depth reaches 280 Mpts.The waveform capture rate is over 200000 wfms / s.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TM935.3

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本文編號：2036468