【摘要】：計(jì)算機(jī)技術(shù)的發(fā)展,帶來(lái)的是各種數(shù)據(jù)量的暴增,而大量數(shù)據(jù)如何進(jìn)行穩(wěn)定快速并且安全的傳輸已經(jīng)成為了當(dāng)今研究的熱點(diǎn)。伴隨著各種嵌入式技術(shù)的發(fā)展,安全千兆以太網(wǎng)的設(shè)計(jì)形式也多種多樣。從最簡(jiǎn)單的單片機(jī),到需要較復(fù)雜的嵌入式軟件編程的ARM處理器,再到基于硬件邏輯的FPGA,都可以實(shí)現(xiàn)安全的千兆以太網(wǎng)功能。在一系列的實(shí)現(xiàn)方式中,FPGA由于其集成度高、并行性設(shè)計(jì)、設(shè)計(jì)靈活性等特點(diǎn)在小型化設(shè)備的設(shè)計(jì)中有獨(dú)特的優(yōu)勢(shì)。論文介紹了一種基于FPGA的安全千兆以太網(wǎng)的設(shè)計(jì)方法。采用軟硬件協(xié)同的設(shè)計(jì)方式,利用FPGA邏輯設(shè)計(jì)完成安全千兆以太網(wǎng)的硬件平臺(tái)搭建,并結(jié)合FPGA嵌入式軟件部分,最終實(shí)現(xiàn)數(shù)據(jù)的加密傳輸。文中首先介紹了設(shè)計(jì)中所使用到的技術(shù)理論基礎(chǔ),包括FPGA的內(nèi)部結(jié)構(gòu)特點(diǎn)、AES算法的實(shí)現(xiàn)基礎(chǔ)和具體結(jié)構(gòu)以及所使用到的精簡(jiǎn)TCP/IP協(xié)議棧模型。并且對(duì)所使用到的MAC控制器和PHY芯片進(jìn)行了深入的研究。在此基礎(chǔ)上,設(shè)計(jì)了基于MAC控制器的自定義數(shù)據(jù)鏈路層IP核,采用自定義異步AXI-FIFO的方式保證在跨時(shí)鐘域傳輸?shù)倪^(guò)程中,數(shù)據(jù)的完整性和可靠性。為了保證數(shù)據(jù)的安全性,系統(tǒng)中采用自定義AES算法IP核。為了保證AES算法加解密的密鑰安全性,結(jié)合FPGA硬件設(shè)計(jì)的特點(diǎn),使用振蕩器產(chǎn)生真隨機(jī)數(shù)作為加解密密鑰;為了節(jié)省FPGA的邏輯資源,采用模塊復(fù)用的方式,將AES加密與解密模塊進(jìn)行了統(tǒng)一的處理。在完成關(guān)鍵硬件模塊設(shè)計(jì)的基礎(chǔ)上,對(duì)LWIP的源碼進(jìn)行移植,并且針對(duì)設(shè)計(jì)需要,對(duì)底層網(wǎng)絡(luò)接口相關(guān)代碼進(jìn)行了重新的設(shè)計(jì)。在應(yīng)用層,設(shè)計(jì)實(shí)現(xiàn)自定義的數(shù)據(jù)接收與發(fā)送函數(shù),并對(duì)接收到的數(shù)據(jù)打印校驗(yàn)。最后,為了系統(tǒng)調(diào)試方便,先對(duì)硬件模塊進(jìn)行模塊化測(cè)試,針對(duì)自定義IP核測(cè)試時(shí),通過(guò)設(shè)計(jì)TestBech測(cè)試用例,自定義產(chǎn)生所要發(fā)送的數(shù)據(jù)。自定義IP核測(cè)試成功之后,再進(jìn)行系統(tǒng)的板級(jí)測(cè)試。通過(guò)板級(jí)測(cè)試,證明本文所設(shè)計(jì)的千兆以太網(wǎng)可以實(shí)現(xiàn)數(shù)據(jù)的加密傳輸;通過(guò)分析FPGA內(nèi)部的資源損耗情況,可以得到該設(shè)計(jì)沒(méi)有使用到任何特殊的嵌入式IP核,并且明顯的減少了FPGA內(nèi)部邏輯資源的消耗。
[Abstract]:The development of computer technology has brought about the sudden increase of all kinds of data, and how to transmit a large number of data stably, quickly and safely has become the focus of current research. With the development of various embedded technologies, the design forms of secure Gigabit Ethernet are also various. From the simplest single chip microcomputer to the ARM processor which needs more complex embedded software programming, to the FPGA, based on hardware logic, the secure Gigabit Ethernet function can be realized. Among a series of implementation methods, FPGA has unique advantages in the design of miniaturized equipment because of its high integration, parallelism design, design flexibility and so on. This paper introduces a design method of secure Gigabit Ethernet based on FPGA. The hardware platform of secure Gigabit Ethernet is designed by using FPGA logic, and the encryption transmission of data is realized by combining the embedded software part of FPGA. In this paper, the technical theoretical basis used in the design is introduced, including the internal structure characteristics of FPGA, the implementation basis and concrete structure of AES algorithm, and the simplified TCP/IP protocol stack model used. The MAC controller and PHY chip are deeply studied. On this basis, a custom data link layer IP core based on MAC controller is designed, and the custom asynchronous AXI-FIFO is used to ensure the integrity and reliability of the data in the process of cross-clock domain transmission. In order to ensure the security of the data, the custom AES algorithm IP core is used in the system. In order to ensure the key security of AES algorithm encryption and decryption, combined with the characteristics of FPGA hardware design, the oscillator is used to generate true random numbers as encryption and decryption keys. In order to save the logic resources of FPGA, the AES encryption and decryption modules are processed uniformly by module reuse. On the basis of completing the design of the key hardware module, the source code of LWIP is ported, and the code related to the underlying network interface is redesigned according to the design needs. In the application layer, a custom data receiving and sending function is designed and implemented, and the received data is printed and verified. Finally, in order to debug the system conveniently, the hardware module is tested modularize. When the custom IP core test case is designed, the TestBech test case is designed to generate the data to be sent. After the custom IP core test is successful, then the board level test of the system is carried out. Through board level test, it is proved that the Gigabit Ethernet designed in this paper can realize the encrypted transmission of data, and by analyzing the resource loss in FPGA, we can get that the design does not use any special embedded IP core, and obviously reduces the consumption of logic resources in FPGA.
【學(xué)位授予單位】：杭州電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP393.11

【相似文獻(xiàn)】

相關(guān)期刊論文 前10條

1 孫雪俊,周祖成;千兆以太網(wǎng)技術(shù)及其進(jìn)展[J];電子技術(shù)應(yīng)用;2000年07期

2 ;思科千兆以太網(wǎng)在證券行業(yè)中的成功應(yīng)用[J];上海微型計(jì)算機(jī);2000年51期

3 T.C.Tan;;千兆以太網(wǎng)援手六類[J];每周電腦報(bào);2000年03期

4 ;千兆以太網(wǎng)[J];電子科技;2001年02期

5 王曉莉;千兆以太網(wǎng)技術(shù)綜述[J];呼倫貝爾學(xué)院學(xué)報(bào);2001年03期

6 子晨;21世紀(jì)日本學(xué)校千兆以太網(wǎng)的應(yīng)用技術(shù)研討會(huì)將在滬召開(kāi)[J];工程設(shè)計(jì)CAD與智能建筑;2001年12期

7 是云冰,李之棠;千兆以太網(wǎng)傳輸線路的研究[J];湖北師范學(xué)院學(xué)報(bào)(自然科學(xué)版);2001年02期

8 劉暢;千兆以太網(wǎng)卡趨向小型化[J];互聯(lián)網(wǎng)周刊;2001年31期

9 石淑華,王青;千兆以太網(wǎng)技術(shù)發(fā)展的分析[J];福建電腦;2002年08期

10 林重頂;應(yīng)用千兆以太網(wǎng)實(shí)現(xiàn)e生活[J];市場(chǎng)與電腦;2002年Z1期

相關(guān)會(huì)議論文 前10條

1 吳武雄;;千兆以太網(wǎng)交換技術(shù)在高速公路上的應(yīng)用[A];中國(guó)高速公路管理學(xué)術(shù)論文集（2009卷）[C];2009年

2 趙靜;張來(lái)保;;千兆以太網(wǎng)技術(shù)的應(yīng)用[A];中國(guó)航海學(xué)會(huì)船舶機(jī)電與通信導(dǎo)航專業(yè)委員會(huì)2002年學(xué)術(shù)年會(huì)論文集（通信導(dǎo)航分冊(cè)）[C];2002年

3 呂小平;向健勇;黃河清;唐小峰;;基于千兆以太網(wǎng)的高速數(shù)據(jù)采集系統(tǒng)設(shè)計(jì)[A];2008'中國(guó)信息技術(shù)與應(yīng)用學(xué)術(shù)論壇論文集（二）[C];2008年

4 陳曄峰;;在第五類雙絞線上實(shí)現(xiàn)千兆以太網(wǎng)[A];第五屆全國(guó)優(yōu)秀青年氣象科技工作者學(xué)術(shù)研討會(huì)學(xué)術(shù)論文集[C];2002年

5 翁玉芬;方建濱;車永剛;王正華;;All-to-all在千兆以太網(wǎng)集群上的性能分析[A];2009全國(guó)計(jì)算機(jī)網(wǎng)絡(luò)與通信學(xué)術(shù)會(huì)議論文集[C];2009年

6 江榕;;千兆以太網(wǎng)及在SDH上的應(yīng)用[A];全國(guó)第十次光纖通信暨第十一屆集成光學(xué)學(xué)術(shù)會(huì)議（OFCIO’2001）論文集[C];2001年

7 春增軍;;不同廠商千兆以太網(wǎng)設(shè)備互聯(lián)關(guān)鍵技術(shù)分析[A];廣東省電機(jī)工程學(xué)會(huì)2003-2004年度優(yōu)秀論文集[C];2005年

8 徐o，

本文編號(hào)：2498866