本文關(guān)鍵詞：CMOS溫度傳感器的研究與設(shè)計　出處：《東南大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： CMOS溫度傳感器 寄生雙極型晶體管 斬波 動態(tài)匹配 Σ-△ADC

【摘要】：溫度傳感器在醫(yī)療設(shè)備、消費(fèi)性電子和工業(yè)控制等領(lǐng)域都不可或缺。相比于傳統(tǒng)的溫度傳感器,集成的CMOS溫度傳感器體積更小、功耗更低、易于集成且可以直接與數(shù)字系統(tǒng)相連,其應(yīng)用前景將更加廣泛。本文設(shè)計的CMOS溫度傳感器采用TSMC 65nm LP CMOS工藝,基于偏置在不同電流密度下的兩個雙極型晶體管的基極-射極電壓差△VBE與絕對溫度成正比的特性,利用模數(shù)轉(zhuǎn)換器將該電壓差進(jìn)行精確量化,最終得到溫度的數(shù)字輸出。本文分析了 CMOS工藝下寄生雙極型晶體管的溫度特性,并對溫度傳感器中的各種非理想因素造成的誤差進(jìn)行了詳細(xì)的討論,其中包括|VBE|的非線性、有限電流增益片和各種失調(diào)(包括運(yùn)放的失調(diào)、電流鏡的失配等)等所引起的誤差,并給出了相應(yīng)的解決方案。針對有限電流增益β采用了電流偏置電路,針對運(yùn)放的失調(diào)采用了斬波技術(shù),針對電流鏡的失配采用了動態(tài)匹配技術(shù)等。由于在實際應(yīng)用中,對溫度測量的速度要求較低,而對精度要求較高,本文采用12位一階Σ-△ADC來進(jìn)行量化工作;Σ-△ADC中的積分器采用了帶增益提高技術(shù)的兩級運(yùn)放,仿真結(jié)果顯示,其低頻增益達(dá)到108dB。整個電路芯片面積為0.588mm×0.536mm,后仿真結(jié)果表明:當(dāng)電源電壓為1.2V,輸入?yún)⒖紩r鐘為400kHz時,在TT工藝角下,芯片總體功耗為1.25mW,溫度誤差在0℃到60℃的測溫范圍內(nèi)達(dá)到了±0.47℃;在SS和FF工藝角下,溫度誤差在0℃到60℃的測溫范圍內(nèi)小于±1.46℃。
[Abstract]:Temperature sensors are indispensable in medical devices, consumer electronics and industrial control. Compared with traditional temperature sensors, integrated CMOS temperature sensors are smaller in size and lower in power consumption. It is easy to integrate and can be directly connected with digital system, and its application prospect will be more extensive. The CMOS temperature sensor designed in this paper adopts TSMC 65nm LP CMOS process. Based on the characteristic that the base-emitter voltage difference (VBE) of two bipolar transistors with bias at different current density is proportional to the absolute temperature, the voltage difference is accurately quantized by A / D converter. Finally, the digital output of temperature is obtained. The temperature characteristics of parasitic bipolar transistor in CMOS process are analyzed, and the error caused by various non-ideal factors in temperature sensor is discussed in detail. It includes the nonlinearity of VBE, the error caused by finite current gain plate and various misalignment (including the mismatch of current mirror and so on). The current bias circuit is used for finite current gain 尾 and chopping technology is used for the misalignment of operational amplifier. The dynamic matching technology is used for the mismatch of the current mirror. Because in the practical application, the speed of the temperature measurement is lower, but the precision is higher. In this paper, 12-bit first order 危-ADC is used for quantization. The integrator in 危-ADC adopts two-stage operational amplifier with gain enhancement technique. The simulation results show that. The low frequency gain reaches 108 dB and the whole chip area is 0.588mm 脳 0.536mm. The simulation results show that when the voltage of power supply is 1.2V. When the input reference clock is 400kHz, the overall power consumption of the chip is 1.25 MW at the TT processing angle, and the temperature error is 鹵0.47 鈩，

本文編號：1378480