【摘要】：在計(jì)算機(jī)網(wǎng)絡(luò)技術(shù)蓬勃發(fā)展之際，基于計(jì)算機(jī)網(wǎng)絡(luò)的應(yīng)用型服務(wù)得到了飛速的發(fā)展，互聯(lián)網(wǎng)信息的安全性引起了研究領(lǐng)域和商業(yè)領(lǐng)域的共同關(guān)注。盡管目前加密的手段種類繁雜，并且在各行各業(yè)中都已經(jīng)形成了自己的規(guī)范體系，但安全問(wèn)題仍然是信息時(shí)代的重要議題。由于網(wǎng)絡(luò)發(fā)展的速度快于數(shù)據(jù)安全思想，因此在網(wǎng)絡(luò)被廣泛應(yīng)用的今天，安全問(wèn)題也愈發(fā)突出。大量敏感信息通過(guò)計(jì)算機(jī)網(wǎng)絡(luò)進(jìn)行交換，加之網(wǎng)絡(luò)的開(kāi)放性，使用戶面對(duì)信息的安全、高效的傳輸表示了迫切的需求。AES算法可以很好地解決數(shù)據(jù)的保密性防護(hù)和認(rèn)證等方面存在的問(wèn)題。因此對(duì)AES算法的安全性問(wèn)題進(jìn)行進(jìn)一步的探索具有重大的研究意義。 論文對(duì)AES高級(jí)密鑰算法的理論層和實(shí)現(xiàn)層進(jìn)行了研究。論文首先詳細(xì)介紹了AES算法的基本原理和現(xiàn)有的有效攻擊方法。然后針對(duì)AES算法中出現(xiàn)的仿射變換周期過(guò)短，迭代輸出周期無(wú)法充滿空間以及正向S盒仿射變換中數(shù)學(xué)表達(dá)式項(xiàng)數(shù)過(guò)少等問(wèn)題，提出了基于AES算法中S盒的改進(jìn)方法。最后提出了基于FPGA的AES加密解密系統(tǒng)設(shè)計(jì)方案，并通過(guò)ISE開(kāi)發(fā)工具自帶的ISim軟件對(duì)系統(tǒng)的加密解密功能進(jìn)行了仿真驗(yàn)證。 論文中提出的S盒改進(jìn)方法中，采用91組仿射變換對(duì)構(gòu)建基本庫(kù)，增強(qiáng)了AES算法的抗基于窮舉法攻擊的能力，另采用二階段仿射變換將仿射變換周期提高至16，迭代輸出周期提高至255，正向S盒變換中S盒仿射變化函數(shù)的數(shù)學(xué)表達(dá)式項(xiàng)數(shù)提高至255，增強(qiáng)了AES算法的抗基于數(shù)學(xué)特性攻擊的能力。在FPGA設(shè)計(jì)時(shí)，使用Xilinx公司的ISE開(kāi)發(fā)套件，硬件開(kāi)發(fā)板選擇的是Xilinx公司的Spartan3ADSP系列，并確定基于AES算法的加密系統(tǒng)設(shè)計(jì)采用基于迭代的反饋模式。AES加密解密系統(tǒng)的設(shè)計(jì)包括對(duì)字節(jié)變換、行變換、列混淆、密鑰加和密鑰擴(kuò)展等五個(gè)核心模塊的設(shè)計(jì)，，以及對(duì)整體控制模塊的設(shè)計(jì)。最終仿真后的數(shù)據(jù)表明，設(shè)計(jì)能夠完成基于AES算法加密解密的功能，進(jìn)而證實(shí)算法整體的正確性，實(shí)現(xiàn)了預(yù)期所要求的算法改良目的。
[Abstract]:With the rapid development of computer network technology, the application service based on computer network has been developed rapidly, and the security of Internet information has attracted the common attention of both the research field and the commercial field. Although the types of encryption methods are complex and their own normative systems have been formed in various industries, security is still an important issue in the information age. Because the development of network is faster than the idea of data security, today, when the network is widely used, the security problem is becoming more and more prominent. A large number of sensitive information is exchanged through the computer network, coupled with the openness of the network, which makes users face the security of information and express the urgent need for efficient transmission. AES algorithm can solve the problems existing in the confidentiality protection and authentication of data. Therefore, it is of great significance to further explore the security of AES algorithm. In this paper, the theoretical layer and implementation layer of AES advanced key algorithm are studied. Firstly, the basic principle of AES algorithm and the existing effective attack methods are introduced in detail. Then, an improved method based on AES algorithm is proposed to solve the problems of affine transformation period in AES algorithm, which is too short, the iterative output period can not be filled with space, and the number of mathematical expressions in forward S-box affine transformation is too small. Finally, the design scheme of AES encryption and decryption system based on FPGA is put forward, and the encryption and decryption function of the system is simulated and verified by the ISim software of ISE development tool. In the improved S-box method proposed in this paper, 91 groups of affine transformation pairs are used to construct the basic library, which enhances the ability of AES algorithm to resist the attack based on exhaustive method. In addition, the affine transformation period is increased to 16, the iterative output period is increased to 255, and the number of mathematical expression items of S-box affine change function in forward S-box transformation is increased to 255. the ability of AES algorithm to resist attacks based on mathematical characteristics is enhanced. In the design of FPGA, using the ISE development suite of Xilinx company, the hardware development board selects the Spartan3ADSP series of Xilinx company, and determines that the encryption system based on AES algorithm adopts iterative feedback mode. The design of FPGA encryption and decryption system includes the design of five core modules, such as byte transformation, row transformation, column confusion, key addition and key expansion, as well as the design of the whole control module. The final simulation data show that the design can complete the encryption and decryption function based on AES algorithm, and then verify the correctness of the algorithm as a whole, and achieve the expected purpose of algorithm improvement.
【學(xué)位授予單位】：北京工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN918.4;TN791

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 王烽;;網(wǎng)絡(luò)數(shù)據(jù)庫(kù)應(yīng)用系統(tǒng)安全研究[J];信息安全與技術(shù);2011年01期

2 林連冬;馬惠珠;溫少波;;基于FPGA技術(shù)的RC6改進(jìn)算法研究[J];電測(cè)與儀表;2008年11期

3 魏志恒;姚國(guó)清;;AES算法的分析與實(shí)現(xiàn)[J];電腦編程技巧與維護(hù);2009年10期

4 韋永壯;蔣留兵;;高級(jí)加密標(biāo)準(zhǔn)AES算法的教學(xué)思路探索[J];大眾科技;2012年03期

5 馮國(guó)柱,李超,多磊,謝端強(qiáng),戴清平;變型的Rijndael及其差分和統(tǒng)計(jì)特性[J];電子學(xué)報(bào);2002年10期

6 亓靜;張坤;;析數(shù)據(jù)加密技術(shù)[J];硅谷;2008年22期

7 張國(guó)勇;;高級(jí)加密標(biāo)準(zhǔn)(AES)算法研究及實(shí)現(xiàn)[J];湖北師范學(xué)院學(xué)報(bào)(自然科學(xué)版);2006年02期

8 王紅珍;張根耀;李竹林;;AES算法及安全性研究[J];信息技術(shù);2011年09期

9 唐琰琰,惲俊;高級(jí)加密標(biāo)準(zhǔn)AES的快速實(shí)現(xiàn)[J];華南金融電腦;2005年07期

10 張新賀;張?jiān)氯A;劉鴻雁;;基于FPGA的16位數(shù)據(jù)路徑的AES IP核[J];計(jì)算機(jī)工程;2009年24期

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