發(fā)布時間：2019-05-30 08:29

【摘要】：電源管理芯片廣泛應用于電子產品中,傳統(tǒng)的電源管理IC主要采用模擬的控制方式來實現(xiàn),但是模擬電源易老化,可移植性差,不易集成等缺點使得模擬電源在高端市場的應用受到了制約。數(shù)字電源以其高集成度,可移植性強和高精度等優(yōu)點在更低的輸出電壓,更寬范圍的負載以及各種電源同步管理等高端市場逐漸嶄露頭角。本文的研究就是針對數(shù)字電源來展開,眾所周知,數(shù)字比例-積分-差分器(Digital Proportion Integral Differential,DPID)和數(shù)字脈寬調制器(Digital Pulse Width Modulator)是數(shù)字電源中兩個最關鍵的模塊,DPID用于對系統(tǒng)進行補償,從而保證系統(tǒng)穩(wěn)定,DPWM用于將表示占空比信息的DPID碼轉換成周期一定的方波信號。所以,有效的補償網(wǎng)絡和高精度、高線性度的DPWM對數(shù)字電源系統(tǒng)的穩(wěn)定來說至關重要。本文創(chuàng)新的地方在于優(yōu)化了DPID的Verilog代碼,消除了傳統(tǒng)DPID模塊產生的毛刺,并且完成了從前端到后端的設計;另外,本文還提出了一種基于混合型數(shù)字脈寬調制器(HDPWM)的帶延遲線二分法校準機制的新電路,該電路引入的二分算法對HDPWM中延遲線部分進行校準,保證延遲線中每相鄰兩個延遲單元的延遲信息相同,從而保證高精度的前提下能有效地提高DPWM的線性度。文中首先詳細介紹了數(shù)字DC-DC變換器的設計方法學、基本原理以及離散域模型,然后介紹了DPID模塊和DPWM模塊從前端到后端的設計,最后仿真驗證了DPWM的功能和數(shù)字電源的功能。對DPID模塊和DPWM模塊采用了全數(shù)字設計流程,借助Synopsys公司的EDA工具實現(xiàn)了系統(tǒng)時鐘為32MHz的9-bit DPWM,該DPWM應用于開關頻率為2MHz的數(shù)字DC-DC變換器。該DPWM模塊在0.13μm CMOS工藝下實現(xiàn),最大差分非線性(DNL)只有0.136LSB,積分非線性(INL)為0.15LSB。本文最終實現(xiàn)的數(shù)字DC-DC變換器輸入電壓范圍為2.7V~4.2V,輸出電壓為0.7V~1.8V。
[Abstract]:Power management chip is widely used in electronic products. The traditional power management IC is mainly realized by analog control, but the analog power supply is easy to age and has poor portability. It is not easy to integrate and other shortcomings, so that the application of analog power supply in the high-end market is restricted. With its advantages of high integration, portability and high precision, digital power supply has gradually emerged in the high-end market, such as lower output voltage, wider range of load and various power supply synchronous management. The research in this paper is aimed at digital power supply. As we all know, digital proportional integral differential (Digital Proportion Integral Differential,DPID) and digital pulse width modulator (Digital Pulse Width Modulator) are the two most critical modules in digital power supply. DPID is used to compensate the system to ensure the stability of the system. DPWM is used to convert the DPID code representing duty cycle information into square wave signal with a certain period. Therefore, effective compensation network and high precision and high linearity DPWM are very important to the stability of digital power supply system. The innovation of this paper is to optimize the Verilog code of DPID, eliminate the burr produced by the traditional DPID module, and complete the design from the front to the back end. In addition, a new circuit with delay line dichotometry calibration mechanism based on hybrid digital pulse width modulator (HDPWM) is proposed in this paper. The dichotometry algorithm introduced in this circuit calibrates the delay line part of HDPWM. It is guaranteed that the delay information of each two adjacent delay units in the delay line is the same, so that the linearity of DPWM can be effectively improved under the premise of high precision. In this paper, the design methodology, basic principle and discrete domain model of digital DC-DC converter are introduced in detail, and then the design of DPID module and DPWM module from front to back end is introduced. Finally, the function of DPWM and the function of digital power supply are verified by simulation. The all-digital design flow is adopted for DPID module and DPWM module, and the 9-bit DPWM, with system clock 32MHz is realized with the help of EDA tool of Synopsys Company. The DPWM is applied to digital DC-DC converter with switching frequency 2MHz. The DPWM module is implemented in 0.13 渭 m CMOS process. The maximum differential nonlinear (DNL) is only 0.136LSB, and the integral nonlinear (INL) is 0.15LSB. The input voltage range of the digital DC-DC converter is 2.7 V 鈮，

本文編號：2488682