【摘要】：目前的各種體制的雷達,如機載雷達,艦載雷達,星載雷達,地面雷達等,若想做到很高的整體性能指標,就需要非常強的信號處理和數(shù)據(jù)處理能力。雷達系統(tǒng)所涉及的信號處理技術(shù)通常都具有數(shù)據(jù)量大、處理任務(wù)復雜、重復運算量大以及實時處理等特點。 本文結(jié)合雷達系統(tǒng)的應(yīng)用,探討了一種基于6678多核DSP以及sys/bios實時操作系統(tǒng)的雷達信號處理解決方案。首先對本文所使用的二相編碼發(fā)射信號進行了設(shè)計與仿真,并分別從其時域和頻域分析二相編碼信號的特點。其次,對所要進行的雷達信號處理流程進行了論述并給出仿真。然后給出的是6678DSP芯片的簡要介紹以及開發(fā)流程,對DSP的線程、EDMA3、多核通信的模塊進行了設(shè)計,接著又基于DSP實現(xiàn)了之前仿真的雷達信號處理流程的各個模塊,并給出實現(xiàn)結(jié)果,與仿真進行對比,驗證了實現(xiàn)方案的可行性。 本文在最后論述了整個系統(tǒng)的調(diào)試過程,首先設(shè)計了調(diào)試所需的TargetConfiguration和Platform文件,并描述了其在系統(tǒng)中發(fā)揮的作用,之后分別調(diào)試了EDMA3和多核通信模塊,驗證了其可行性,并計算了整個過程所耗時間,驗證了系統(tǒng)的實時性。
[Abstract]:At present, all kinds of radar, such as airborne radar, shipborne radar, satellite radar, ground radar and so on, need very strong signal processing and data processing ability if they want to achieve high overall performance index. The signal processing technology involved in radar system usually has the characteristics of large amount of data, complex processing tasks, large amount of repeated computation and real-time processing. Combined with the application of radar system, this paper discusses a radar signal processing solution based on 6678 multi-core DSP and sys/bios real-time operating system. Firstly, the two-phase coded transmit signal used in this paper is designed and simulated, and the characteristics of the two-phase coded signal are analyzed from its time domain and frequency domain, respectively. Secondly, the radar signal processing flow is discussed and the simulation is given. Then it gives a brief introduction of 6678DSP chip and the development flow. The thread of DSP and the module of EDMA3, multi-core communication are designed, and then each module of radar signal processing flow simulated before is realized based on DSP. The implementation results are given and compared with the simulation to verify the feasibility of the implementation scheme. At the end of this paper, the debugging process of the whole system is discussed. Firstly, the TargetConfiguration and Platform files needed for debugging are designed, and their functions in the system are described. Then, the EDMA3 and multi-core communication modules are debugged respectively, and their feasibility is verified. The time spent in the whole process is calculated, and the real-time performance of the system is verified.
【學位授予單位】：南京理工大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN957.51

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