后向投影算法并行計(jì)算系統(tǒng)設(shè)計(jì)
[Abstract]:The backward projection (back projection, BP) radar imaging algorithm is a kind of radar imaging algorithm based on time domain processing. It has good robustness and is suitable for airborne arbitrary motion and non-uniform aperture synthetic aperture radar imaging. Although the BP algorithm can be used in SAR imaging without any approximation, its computational efficiency is very low. The computation quantity is in direct proportion to the number of echo pulses and the number of pixels in the target image, so it is very large in the application of high resolution imaging. The operation time is very long, so how to improve the efficiency of the algorithm becomes an urgent problem. In this paper, the algorithm is optimized from the point of view of parallelization. On the basis of fully analyzing the concurrency characteristics of the algorithm, three parallel optimization methods are proposed, and the hardware and software imaging system based on NoC multi-core is designed, which effectively improves the efficiency of the algorithm. Based on the experimental results of FPGA, two real time imaging schemes are proposed, which provide two approaches for the practical application of the algorithm. In order to accelerate the design efficiency of the multi-core imaging system, the C model and the TLM model of the system are established by C and SystemC firstly, and the whole system architecture is unified from the macro view, and the software and hardware of the system are divided reasonably. In the early stage of hardware and software co-verification, the system design cycle is shortened. Based on the system model, the corresponding hardware and software are designed based on NoC and multi-core architecture. The backprojection operation which has the largest computation and good concurrency in the algorithm is encapsulated into the hardware accelerating kernel. The efficiency of the algorithm is further improved by integrating several accelerating cores. The system chooses ARM processor as the main control core of the subsystem, designs the corresponding parallel software, and finally realizes the high performance computing system of the BP algorithm. The designed system is verified on FPGA. For the target image with the size of 8K*4K, the imaging time without acceleration on the PC is 5 hours and 23 minutes, but the imaging time of the system is only 5 minutes and 10 seconds, and the acceleration ratio is as high as 65 times. The validity of the designed system is verified. Finally, aiming at the problem that the experimental results of 8K*4K size target images on FPGA still can not meet the requirements of real-time imaging applications, this paper gives an analysis and puts forward two effective solutions, which provide an effective solution for the practical application of the system.
【學(xué)位授予單位】:南京大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2014
【分類號(hào)】:TN957.52
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