【摘要】：隨著通信技術(shù)特別是無線通信技術(shù)的飛速發(fā)展,各種不同通信標(biāo)準(zhǔn)和協(xié)議被應(yīng)用于無線通訊領(lǐng)域。同時,基于人們對無線通信領(lǐng)域中低時延、高吞吐率數(shù)據(jù)傳輸?shù)男枨?使得傳輸標(biāo)準(zhǔn)和協(xié)議的更新?lián)Q代變得越來越頻繁,無線通信系統(tǒng)的實(shí)現(xiàn)也變得越來越復(fù)雜。為適應(yīng)這些變化,設(shè)計(jì)并實(shí)現(xiàn)一個標(biāo)準(zhǔn)通用的軟件無線電平臺顯得十分重要。 本文從硬件實(shí)現(xiàn)、接口互聯(lián)標(biāo)準(zhǔn)和系統(tǒng)軟件架構(gòu)三個角度出發(fā),對比和分析了現(xiàn)有通用軟件無線電平臺的實(shí)現(xiàn)方案,并在此基礎(chǔ)上提出了一種基于多核DSP的通用軟件無線電系統(tǒng)平臺設(shè)計(jì)方案。本文研究了當(dāng)前處理器的多核技術(shù),詳細(xì)介紹了KeyStone架構(gòu)下多核處理的相關(guān)軟硬件實(shí)現(xiàn)細(xì)節(jié)。 針對多核DSP的通用軟件無線電系統(tǒng)平臺設(shè)計(jì)方案,本文從硬件和軟件兩個方面著手,詳細(xì)介紹了基于Virtex-6系列FPGA的多通道模擬信號采集前端和多核DSP數(shù)字信號處理后端的具體設(shè)計(jì)細(xì)節(jié)。闡述并實(shí)現(xiàn)了基于RapidIO串行協(xié)議的高速互聯(lián)技術(shù)。 針對硬件電路板設(shè)計(jì)部分,本文從高速PCB設(shè)計(jì)角度出發(fā),詳細(xì)介紹了多層電路板疊層設(shè)計(jì)、電源平面分割、拓?fù)浣Y(jié)構(gòu)選擇和等長走線約束設(shè)置等內(nèi)容。給出了高速ADC采樣芯片、DDR3存儲芯片相關(guān)的約束設(shè)置細(xì)節(jié)和走線實(shí)際延時參數(shù)。
[Abstract]:With the rapid development of communication technology, especially wireless communication technology, various communication standards and protocols have been applied in wireless communication field. At the same time, due to the demand of low delay and high throughput data transmission in wireless communication field, the updating of transmission standards and protocols becomes more and more frequent, and the implementation of wireless communication system becomes more and more complex. In order to adapt to these changes, it is very important to design and implement a standard general software radio platform. From three aspects of hardware implementation, interface interconnection standard and system software architecture, this paper compares and analyzes the implementation schemes of the existing general software radio platform. On this basis, a general software radio system platform based on multi-core DSP is proposed. In this paper, the current multi-core processor is studied, and the hardware and software implementation details of multi-core processing based on KeyStone architecture are introduced in detail. Aiming at the general software radio system platform design of multi-core DSP, this paper starts from two aspects: hardware and software. The design details of multi-channel analog signal acquisition front end and multi-core DSP digital signal processing back-end based on Virtex-6 series FPGA are introduced in detail. The technology of high speed interconnection based on RapidIO serial protocol is described and realized. Aiming at the design of hardware circuit board, this paper introduces in detail the design of multilayer circuit board, power plane partition, topology selection and constraint setting of equal length running line from the point of view of high speed PCB design. The high speed ADC sampling chip, the constraint setting details of DDR3 memory chip and the actual delay parameters are given.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN925

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本文編號：2413765