【摘要】：軟件無線電由于具有可編程性、可重構(gòu)性以及模塊化設(shè)計(jì)等優(yōu)勢(shì),因此基于該平臺(tái)實(shí)現(xiàn)通用數(shù)字通信鏈路,在教學(xué)演示與科研驗(yàn)證中具有現(xiàn)實(shí)可用性和可推廣性。為此,論文基于團(tuán)隊(duì)自主研發(fā)的uSDR軟件無線電平臺(tái)上,設(shè)計(jì)了單載波頻域均衡64QAM數(shù)據(jù)鏈路,并在該平臺(tái)上完成了演示驗(yàn)證。論文的具體內(nèi)容如下:第一,單載波頻域均衡64QAM鏈路的設(shè)計(jì)。從工程實(shí)現(xiàn)的角度研究了該鏈路物理層設(shè)計(jì)的關(guān)鍵技術(shù),根據(jù)項(xiàng)目對(duì)鏈路的功能需求和性能需求,參考其它常用通信鏈路的設(shè)計(jì)方案,設(shè)計(jì)出該鏈路物理層幀結(jié)構(gòu)。論文設(shè)計(jì)鏈路的每幀持續(xù)時(shí)長10ms,數(shù)據(jù)業(yè)務(wù)速率為32.8704Mbps。本文將整個(gè)鏈路數(shù)據(jù)信號(hào)處理流程分為發(fā)射機(jī)與接收機(jī)兩部分,給出了各關(guān)鍵模塊的詳細(xì)設(shè)計(jì)方案。第二,單載波頻域均衡64QAM鏈路的圖形化開發(fā)。論文采用了Xilinx提供的圖形化開發(fā)工具System Generator完成了鏈路的開發(fā)。在FPGA上實(shí)現(xiàn)了包括鏈路的上下變頻模塊、時(shí)頻同步模塊、調(diào)制編碼模塊等關(guān)鍵模塊,并完成了全鏈路的誤碼率性能和時(shí)間同步性能的仿真。第三,單載波頻域均衡64QAM鏈路的演示驗(yàn)證。在團(tuán)隊(duì)自主研發(fā)的軟件無線電平臺(tái)上完成了鏈路的功能測(cè)試與性能測(cè)試(包括文件傳輸測(cè)試、誤碼率測(cè)試、時(shí)間同步測(cè)試和抗頻偏性能測(cè)試),基本滿足了鏈路的設(shè)計(jì)指標(biāo),在性能與資源消耗取舍上選擇了一個(gè)比較好的平衡點(diǎn)。論文基于軟件無線電平臺(tái)實(shí)現(xiàn)了單載波頻域均衡64QAM鏈路,提供了通信系統(tǒng)常見信號(hào)處理模版,可用于通信教學(xué)演示與科研驗(yàn)證,豐富了軟件無線電通信鏈路庫,為以后在軟件無線電平臺(tái)上進(jìn)行更復(fù)雜的通信鏈路開發(fā)提供了參考。
[Abstract]:Because software radio has the advantages of programmability reconfiguration and modularization design it realizes the universal digital communication link based on the platform and has practical availability and extensibility in teaching demonstration and scientific research verification. Therefore, based on the uSDR software radio platform developed by the team, a single carrier frequency domain equalization 64QAM data link is designed and demonstrated on the platform. The main contents of this paper are as follows: first, the design of single carrier frequency domain equalization 64QAM link. The key technology of the physical layer design of the link is studied from the point of view of engineering implementation. According to the functional and performance requirements of the link, the frame structure of the physical layer of the link is designed according to the design schemes of other commonly used communication links. In this paper, the duration of each frame is 10 msand the data traffic rate is 32.8704 Mbps. In this paper, the whole link data signal processing flow is divided into transmitter and receiver, and the detailed design scheme of each key module is given. Second, the graphical development of single carrier frequency domain equalization 64QAM link. In this paper, System Generator, a graphical development tool provided by Xilinx, is used to complete the link development. The key modules such as up-down conversion module, time-frequency synchronization module, modulation and coding module are implemented on FPGA, and the BER performance and time synchronization performance of the whole link are simulated. Third, the demonstration of single carrier frequency domain equalization 64QAM link. The function test and performance test (including file transmission test, bit error rate test, time synchronization test and anti-frequency offset performance test) of the link are completed on the software radio platform independently developed by the team, which basically meets the design index of the link. A better balance is chosen between performance and resource consumption. Based on the software radio platform, this paper realizes the single carrier frequency domain equalization 64QAM link, provides the common signal processing template of the communication system, can be used for communication teaching demonstration and scientific research verification, and enriches the software radio communication link library. It provides a reference for the further development of more complex communication links on the software radio platform.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN92

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本文編號(hào)：2383072