基于FPGA的單片SDRAM視頻讀寫乒乓操作設(shè)計與優(yōu)化
發(fā)布時間：2018-12-14 19:29
【摘要】：在工業(yè)生產(chǎn)中,很多控制設(shè)備利用液晶顯示屏顯示設(shè)備當前狀態(tài),當外部干擾使數(shù)據(jù)發(fā)送時鐘錯誤或者數(shù)據(jù)的采集與顯示速度不同,顯示屏會產(chǎn)生畫面偏移或者遲鈍的現(xiàn)象。針對該問題,本文提出一種基于FPGA的單片SDRAM的視頻緩存控制,在研究SDRAM的結(jié)構(gòu)基礎(chǔ)上,編寫Verilog語言實現(xiàn)單片SDRAM的乒乓讀寫操作,利用讀寫時差和SDRAM的BANK切換存儲,使用FIFO實現(xiàn)異步時鐘的數(shù)據(jù)交換,提高數(shù)據(jù)吞吐量,當數(shù)據(jù)時鐘受干擾時能自動刷新。本文對更功能模塊進行分析,根據(jù)設(shè)計要求選擇合適的FPGA和SDRAM芯片,并根據(jù)芯片設(shè)計制作PCB電路板,搭建硬件調(diào)試平臺,利用一個800×480像素LCD液晶顯示屏顯示畫面,畫面穩(wěn)定流暢。
[Abstract]:In industrial production, many control devices use liquid crystal display screen to display the current state of the device. When the external interference makes the data send clock error or the data acquisition and display speed is different, the display screen will produce the phenomenon of picture offset or dullness. To solve this problem, this paper proposes a video buffer control based on FPGA for monolithic SDRAM. On the basis of studying the structure of SDRAM, we write the Verilog language to realize the ping-pong reading and writing operation of single SDRAM, and use the time difference of reading and writing and BANK of SDRAM to switch storage. FIFO is used to realize the data exchange of asynchronous clock to improve the data throughput and refresh automatically when the data clock is disturbed. In this paper, the more functional modules are analyzed, the appropriate FPGA and SDRAM chips are selected according to the design requirements, and the PCB circuit board is designed according to the design of the chip. The hardware debugging platform is built, and a 800 脳 480 pixel LCD screen is used to display the screen. The picture is stable and smooth.
【作者單位】： 五邑大學信息工程學院;
【分類號】：TN873.93
，
本文編號：2379191
[Abstract]:In industrial production, many control devices use liquid crystal display screen to display the current state of the device. When the external interference makes the data send clock error or the data acquisition and display speed is different, the display screen will produce the phenomenon of picture offset or dullness. To solve this problem, this paper proposes a video buffer control based on FPGA for monolithic SDRAM. On the basis of studying the structure of SDRAM, we write the Verilog language to realize the ping-pong reading and writing operation of single SDRAM, and use the time difference of reading and writing and BANK of SDRAM to switch storage. FIFO is used to realize the data exchange of asynchronous clock to improve the data throughput and refresh automatically when the data clock is disturbed. In this paper, the more functional modules are analyzed, the appropriate FPGA and SDRAM chips are selected according to the design requirements, and the PCB circuit board is designed according to the design of the chip. The hardware debugging platform is built, and a 800 脳 480 pixel LCD screen is used to display the screen. The picture is stable and smooth.
【作者單位】： 五邑大學信息工程學院;
【分類號】：TN873.93
，
本文編號：2379191
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