【摘要】：隨著高速無線互聯(lián)應用場景的增加,人們對短距離通信技術的傳輸速率要求越來越高,現(xiàn)有的處于低頻段的WiFi技術很難滿足千兆傳輸速率,因此具有高達7GHz免授權頻譜的60GHz毫米波頻段日益引起了大家的關注。在接收端,射頻RF和基帶是兩個重要的組成部分,其中60GHz射頻技術已經獲得了較好解決而高速低功耗的60GHz基帶技術依然是一個挑戰(zhàn)。本文參照IEEE802.11ad標準,探討了單載波調制下的60GHz接收機基帶算法及部分FPGA實現(xiàn),同時針對高速時間交叉采樣ADC的接口設計和測試也做了一些研究和設計。第一章概述了60GHz的研究背景和研究現(xiàn)狀。分析了60GHz頻段的特點并給出了本文的架構安排。第二章首先從大尺度衰落和小尺度衰落兩方面簡單介紹了60GHz的信道,給出了本設計仿真用的信道參數(shù),其次簡單介紹了IEEE802.11ad的物理層幀結構,同時還介紹了在60GHz基帶中起重要作用的Golay互補序列的相關背景、生成算法和相關器設計。最后介紹了時間交叉采樣ADC的工作原理和模型,并分析了直流偏移、增益失配、時鐘相位失配這三種情況對ADC性能的影響第三章首先給出了一個基于FPGA實現(xiàn)平臺的60GHz基帶的總框架圖,確定ADC采樣速率和FPGA內部電路并行數(shù)。接著描述了數(shù)據(jù)分組和去?2旋轉的兩個小模塊。然后針對幀檢測、載波頻偏同步、信道估計算法、采樣定時同步和均衡算法做了探索和仿真。第四章首先對本設計中60GHz硬件平臺中進行闡述,并對采樣率達3.52Gsample/s高速時間交叉ADC進行研究,主要包括ADC與FPGA接口設計、通道失配校正、ADC參數(shù)測試提取。同時介紹了高速并行Golay序列相關器的FPGA實現(xiàn)方案和測試結果,最后針對60GHz高速并行的傳輸特點,設計了特殊的NCO,比常規(guī)的并行NCO節(jié)省了87.5%的面積。最后一章總結了本文的工作,給出了結論,以及下一步要進行的主要工作。
[Abstract]:With the increase of high speed wireless interconnection applications, the transmission rate of short distance communication technology is becoming more and more high. The existing WiFi technology in low frequency band is difficult to meet the gigabit transmission rate. Therefore, 60GHz millimeter wave band with up to 7GHz-free spectrum has attracted more and more attention. In the receiver, RF and baseband are two important components. Among them, 60GHz RF technology has been solved well, but the 60GHz baseband technology with high speed and low power consumption is still a challenge. Referring to the IEEE802.11ad standard, this paper discusses the baseband algorithm and partial FPGA implementation of 60GHz receiver under single carrier modulation. At the same time, the interface design and test of high speed time cross-sampling ADC are also studied and designed. The first chapter summarizes the research background and research status of 60GHz. The characteristics of 60GHz band are analyzed and the architecture of this paper is given. In the second chapter, the channel of 60GHz is introduced from two aspects: large scale fading and small scale fading, and the channel parameters used in the design and simulation are given. Secondly, the physical layer frame structure of IEEE802.11ad is briefly introduced. At the same time, the background, generation algorithm and correlator design of Golay complementary sequences which play an important role in 60GHz baseband are also introduced. Finally, the working principle and model of time cross sampling ADC are introduced, and the DC offset and gain mismatch are analyzed. The influence of clock Phase mismatch on ADC performance Chapter 3 first gives a general frame diagram of the 60GHz baseband based on the FPGA implementation platform and determines the ADC sampling rate and the parallel number of FPGA internal circuits. Then it describes two small modules of data grouping and de-2 rotation. Then, the frame detection, carrier frequency offset synchronization, channel estimation algorithm, sampling timing synchronization and equalization algorithm are explored and simulated. In the fourth chapter, the 60GHz hardware platform is introduced, and the sampling rate of 3.52Gsample/s high speed time crossover ADC is studied, including the design of ADC and FPGA interface, channel mismatch correction, ADC parameter test and extraction. At the same time, the FPGA implementation scheme and test results of high speed parallel Golay sequence correlator are introduced. Finally, according to the characteristics of 60GHz high speed parallel transmission, the special NCO, is designed to save 87.5% area compared with the conventional parallel NCO. The last chapter summarizes the work of this paper, gives the conclusion, and the main work to be done next.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN928

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本文編號：2377817