相控陣?yán)走_(dá)波束控制技術(shù)研究
發(fā)布時間：2018-12-13 07:20
【摘要】：波控系統(tǒng)是有源相控陣?yán)走_(dá)的重要組成部分,主要作用是形成特定指向、低旁瓣、能規(guī)避特定干擾的波束信號。本論文根據(jù)某型相控陣?yán)走_(dá)項(xiàng)目實(shí)際需求,首先研究和仿真了如何形成規(guī)避特定波束指向干擾信號的零點(diǎn)調(diào)向算法,然后設(shè)計(jì)并且完成了一個能控制T/R模塊幅度和相位參數(shù)的波束控制電路系統(tǒng),最后針對該電路系統(tǒng)FPGA外圍特點(diǎn),將零點(diǎn)調(diào)向算法利用MODESIM進(jìn)行具體功能化實(shí)現(xiàn)。本課題提出了一種新的波控機(jī)硬件實(shí)現(xiàn)方法,該波控機(jī)具有運(yùn)算能力強(qiáng)大、數(shù)據(jù)吞吐能力強(qiáng)的特點(diǎn);零點(diǎn)調(diào)向算法的工程化設(shè)計(jì)方法具有實(shí)現(xiàn)簡便、通用性好的特點(diǎn)。算法仿真部分首先研究了均勻線陣的數(shù)學(xué)模型和波束形成的零點(diǎn)約束條件,利用最小二乘法和拉格朗日算子進(jìn)行最優(yōu)系數(shù)求解,得到了零點(diǎn)調(diào)向系數(shù)求解公式。此外,利用仿真分析了零階約束條件對波束形成的影響,為后續(xù)工程化實(shí)現(xiàn)打下基礎(chǔ)。算法FPGA實(shí)現(xiàn)部分首先對比了零點(diǎn)調(diào)向的幾種常見方法,利用課題算法仿真結(jié)果設(shè)計(jì)出一種基于FPGA實(shí)現(xiàn)的零點(diǎn)調(diào)向方法。為實(shí)現(xiàn)和浮點(diǎn)DSP之間的無縫連接,所有數(shù)據(jù)采用IEEE754標(biāo)準(zhǔn)浮點(diǎn)單精度格式,實(shí)現(xiàn)主要涉及了向量和矩陣的乘加運(yùn)算。底層利用IP核實(shí)現(xiàn)核心算法,采用狀態(tài)機(jī)實(shí)現(xiàn)時序控制,整個過程利用MODESIM與QUARTUS II軟件聯(lián)合完成。波控電路系統(tǒng)實(shí)現(xiàn)部分首先分析和研究了經(jīng)典的波控機(jī)結(jié)構(gòu)組成,然后根據(jù)具體項(xiàng)目要求設(shè)計(jì)了DSP與FPGA混合架構(gòu)的波控系統(tǒng),最后經(jīng)過焊接、調(diào)試后用于實(shí)際工程項(xiàng)目中。波控機(jī)核心運(yùn)算單元采用ADI公司的TS101和ALTERA公司的EP2S90,它們構(gòu)成的運(yùn)算核心具有強(qiáng)大的數(shù)據(jù)處理能力。波控電路系統(tǒng)外圍接口豐富,最多能控制8×8陣元的T/R模塊,能進(jìn)行網(wǎng)絡(luò)和串口的上位機(jī)控制,有超過16個IO命令擴(kuò)展接口。波控電路系統(tǒng)數(shù)據(jù)存儲能力強(qiáng)大,有超過2G×8位的FLASH存儲器可用于標(biāo)校數(shù)據(jù)存儲,以及512K×32位乒乓無縫RAM實(shí)時存儲器。
[Abstract]:Wave control system is an important part of active phased array radar. The main function is to form a specific direction, low sidelobe, and avoid the special interference of the beam signal. According to the actual requirements of a phased array radar project, this paper first studies and simulates how to form a zero-point direction modulation algorithm to avoid the interference signal of a specific beam. Then, a beam-beam control circuit system which can control the amplitude and phase parameters of the T / R module is designed and completed. Finally, according to the peripheral characteristics of the circuit system FPGA, the zeroing algorithm is realized by using MODESIM. In this paper, a new method of realizing the hardware of the wave controller is presented, which has the characteristics of powerful operation ability and strong data throughput, and the engineering design method of the zero direction adjustment algorithm has the characteristics of simple realization and good generality. In the simulation part of the algorithm, the mathematical model of uniform linear array and the zero point constraint condition of beamforming are studied. The optimal coefficient is solved by using least square method and Lagrange operator, and the formula of zero point direction adjustment coefficient is obtained. In addition, the effect of zero order constraint on beamforming is analyzed by simulation. In the part of FPGA implementation, several common methods of zero direction adjustment are compared, and a zero direction adjustment method based on FPGA is designed by using the simulation results of the algorithm. In order to realize the seamless connection between DSP and floating-point, all the data adopt IEEE754 standard floating-point single-precision format, which mainly involves the multiplication and addition of vectors and matrices. In the bottom layer, the core algorithm is realized by IP core, the timing control is realized by state machine, and the whole process is accomplished by MODESIM and QUARTUS II software. In the realization part of the wave control circuit system, the structure of the classical wave control machine is analyzed and studied firstly, and then the wave control system based on the DSP and FPGA hybrid architecture is designed according to the specific project requirements. After welding and debugging, the system is used in the actual engineering project. The core operation unit of the wave control machine is composed of TS101 of ADI Company and EP2S90, of ALTERA Company, which have powerful data processing ability. The wave control circuit system has abundant peripheral interfaces and can control 8 脳 8 array elements of the T / R module at most. It can control the upper computer of network and serial port. There are more than 16 IO command extension interfaces. The data storage ability of the wave control circuit system is very powerful. The FLASH memory with more than 2G 脳 8 bits can be used for calibrating data storage and 512K 脳 32-bit ping-pong seamless RAM real-time memory.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN958.92
本文編號：2376140
[Abstract]:Wave control system is an important part of active phased array radar. The main function is to form a specific direction, low sidelobe, and avoid the special interference of the beam signal. According to the actual requirements of a phased array radar project, this paper first studies and simulates how to form a zero-point direction modulation algorithm to avoid the interference signal of a specific beam. Then, a beam-beam control circuit system which can control the amplitude and phase parameters of the T / R module is designed and completed. Finally, according to the peripheral characteristics of the circuit system FPGA, the zeroing algorithm is realized by using MODESIM. In this paper, a new method of realizing the hardware of the wave controller is presented, which has the characteristics of powerful operation ability and strong data throughput, and the engineering design method of the zero direction adjustment algorithm has the characteristics of simple realization and good generality. In the simulation part of the algorithm, the mathematical model of uniform linear array and the zero point constraint condition of beamforming are studied. The optimal coefficient is solved by using least square method and Lagrange operator, and the formula of zero point direction adjustment coefficient is obtained. In addition, the effect of zero order constraint on beamforming is analyzed by simulation. In the part of FPGA implementation, several common methods of zero direction adjustment are compared, and a zero direction adjustment method based on FPGA is designed by using the simulation results of the algorithm. In order to realize the seamless connection between DSP and floating-point, all the data adopt IEEE754 standard floating-point single-precision format, which mainly involves the multiplication and addition of vectors and matrices. In the bottom layer, the core algorithm is realized by IP core, the timing control is realized by state machine, and the whole process is accomplished by MODESIM and QUARTUS II software. In the realization part of the wave control circuit system, the structure of the classical wave control machine is analyzed and studied firstly, and then the wave control system based on the DSP and FPGA hybrid architecture is designed according to the specific project requirements. After welding and debugging, the system is used in the actual engineering project. The core operation unit of the wave control machine is composed of TS101 of ADI Company and EP2S90, of ALTERA Company, which have powerful data processing ability. The wave control circuit system has abundant peripheral interfaces and can control 8 脳 8 array elements of the T / R module at most. It can control the upper computer of network and serial port. There are more than 16 IO command extension interfaces. The data storage ability of the wave control circuit system is very powerful. The FLASH memory with more than 2G 脳 8 bits can be used for calibrating data storage and 512K 脳 32-bit ping-pong seamless RAM real-time memory.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN958.92
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