【摘要】：低密度奇偶校驗(LDPC)碼是一種逼近香農(nóng)極限的信道編碼,它是由Gallager在1962年首次提出,然而由于受到當(dāng)時技術(shù)的限制,LDPC碼沒能得到重視。直到1996年,LDPC碼才被編碼研究人再次發(fā)現(xiàn),并將其進一步推廣。近幾年,LDPC碼憑借其自身的眾多優(yōu)點,成為第四代移動通信技術(shù)(4G)的信道編碼方案,再次被人們所關(guān)注。近幾年,研究LDPC碼編解碼器硬件實現(xiàn)的學(xué)者大量涌現(xiàn)。由于LDPC碼校驗矩陣結(jié)構(gòu)具有隨機性,因此給硬件實現(xiàn)帶來很大的困難。準(zhǔn)循環(huán)低密度奇偶校檢(QC-LDPC)碼的提出,其獨特的準(zhǔn)循環(huán)特性,降低了編解碼的實現(xiàn)復(fù)雜度。之后,一些學(xué)者和專家基于TPMP算法提出了TDMP類算法,并提出了相應(yīng)的分層解碼算法及其分層解碼結(jié)構(gòu)。此解碼結(jié)構(gòu)能很好的在硬件消耗和解碼性能之間取得平衡,因此成為QC-LDPC解碼器的主流結(jié)構(gòu)。本文首先分析了LDPC和QC-LDPC碼的相關(guān)概念,并重點研究了基于有限域乘群構(gòu)造無短四環(huán)的QC-LDPC碼的方法。其次,重點研究了LDPC碼的幾種常用的軟判決解碼算法,通過軟件仿真確定了歸一化最小和算法校正因子的最優(yōu)解為0.8。通過對各個解碼算法的性能比較與詳細(xì)分析,確定了分層解碼算法為最優(yōu)的硬件實現(xiàn)解碼算法。通過軟件仿真確定了硬件實現(xiàn)時數(shù)據(jù)量化比特數(shù)為7比特。最后,利用Quartus II 9.0軟件,采用Verilog HDL語言,基于自頂向下的模塊設(shè)計方法,對解碼器進行了程序設(shè)計,并在Altera公司StratixII系列的EP2S60F484C4器件上,對所設(shè)計的解碼器進行了布局布線與綜合,利用ModelSim 6.4a軟件進行了仿真測試,驗證了所設(shè)計解碼器功能的正確性。解碼器在最大迭代次數(shù)為5,工作時鐘頻率設(shè)為35MHz時,吞吐率已達(dá)到92.27Mbps。
[Abstract]:Low-density parity check (LDPC) codes are channel codes that approach the Shannon limit, which was first proposed by Gallager in 1962. However, due to the limitations of technology at that time, LDPC codes have not been paid much attention to. It was not until 1996 that LDPC codes were discovered again by coding researchers and further extended. In recent years, LDPC code has become the channel coding scheme of the fourth generation mobile communication technology (4G) by virtue of its many advantages. In recent years, a large number of scholars have emerged to study the hardware implementation of LDPC codec. Due to the randomness of the LDPC code check matrix structure, it is difficult to implement the hardware. The proposed quasi-cyclic low-density parity check (QC-LDPC) codes have unique quasi-cyclic characteristics and reduce the complexity of coding and decoding. After that, some scholars and experts put forward the TDMP class algorithm based on the TPMP algorithm, and put forward the corresponding layered decoding algorithm and its hierarchical decoding structure. This decoding structure can achieve a good balance between hardware consumption and decoding performance, so it becomes the mainstream structure of QC-LDPC decoder. In this paper, the concepts of LDPC and QC-LDPC codes are analyzed, and the method of constructing QC-LDPC codes without short four rings based on finite field multiplicative groups is studied. Secondly, several commonly used soft decision decoding algorithms for LDPC codes are studied, and the optimal solution of normalized minimum and correction factor is determined to be 0.8 by software simulation. By comparing and analyzing the performance of each decoding algorithm, it is determined that the layered decoding algorithm is the best hardware decoding algorithm. Through the software simulation, the quantization bit number of the hardware is determined to be 7 bits. Finally, using Quartus II 9.0 software and Verilog HDL language, based on the top-down module design method, the decoder is programmed and implemented on the EP2S60F484C4 device of StratixII series of Altera Company. The layout, wiring and synthesis of the designed decoder are carried out, and the correctness of the designed decoder is verified by using ModelSim 6.4a software. When the maximum iteration number is 5 and the working clock frequency is set to 35MHz, the throughput has reached 92.27 Mbps.
【學(xué)位授予單位】：南京航空航天大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN911.22
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本文編號：2372793