【摘要】：隨著高清技術(shù)和高速攝像等領(lǐng)域的飛速發(fā)展,人們已不再滿足于現(xiàn)有的圖像精細(xì)程度和低速的刷新率。更高分辨率,更高刷新率的多媒體信息是人們生活需求的發(fā)展趨勢,也是科學(xué)技術(shù)的發(fā)展趨勢。圖像編解碼系統(tǒng)作為高速圖像處理的核心單元,其編解碼能力的好壞,直接影響著多媒體信息的質(zhì)量與傳輸效率。目前數(shù)字圖像處理系統(tǒng)廣泛采用DVI1.0標(biāo)準(zhǔn)接口傳輸數(shù)字視頻。根據(jù)成像系統(tǒng)的需求,本文設(shè)計并實現(xiàn)了一套D-Link DVI高速圖像編解碼系統(tǒng)。該系統(tǒng)以Xilinx Kintex 7 FPGA為核心處理器、以DDR3 SDRAM為存儲設(shè)備,以DVI, VGA為數(shù)據(jù)傳輸接口,解決了成像系統(tǒng)受限于最高像素時鐘只能達(dá)到165MHz,無法傳輸更高幀頻、更高分辨率數(shù)字圖像的問題。該系統(tǒng)內(nèi)部利用流水線設(shè)計思想、查表法、乒乓操作以及MCB控制核實現(xiàn)了DVI雙通道的接收與發(fā)送,視頻圖像實時編碼算法處理,視頻圖像降幀處理和DVI至VGA視頻信號的轉(zhuǎn)換等功能。本文在介紹視頻傳輸接口規(guī)范、核心處理器及存儲器原理的基礎(chǔ)上,詳細(xì)敘述了系統(tǒng)組成、雙鏈路DVI設(shè)計方案、系統(tǒng)關(guān)鍵技術(shù)、硬件電路板制作、編解碼算法邏輯實現(xiàn)和系統(tǒng)整體調(diào)試分析。該系統(tǒng)最大像素時鐘可達(dá)330MHz。
[Abstract]:With the rapid development of high-definition technology and high-speed video, people are no longer satisfied with the existing image fine degree and low speed refresh rate. The multimedia information with higher resolution and higher refresh rate is the development trend of people's living needs, and also the development trend of science and technology. As the core unit of high-speed image processing, image coding and decoding system has a direct impact on the quality and transmission efficiency of multimedia information. At present, DVI1.0 standard interface is widely used in digital image processing system to transmit digital video. According to the requirement of imaging system, this paper designs and implements a D-Link DVI high-speed image coding and decoding system. The system uses Xilinx Kintex 7 FPGA as the core processor, DDR3 SDRAM as the storage device and DVI, VGA as the data transmission interface. The system solves the problem that the maximum pixel clock can only reach 165 MHz, which can not transmit higher frame rate. The problem of higher resolution digital images. The system uses pipeline design idea, table searching method, ping-pong operation and MCB control core to realize the receiving and transmitting of DVI dual channels, and real-time video image coding algorithm processing. Video image frame reduction processing and DVI to VGA video signal conversion and other functions. Based on the introduction of video transmission interface specification, core processor and memory principle, this paper describes in detail the composition of the system, the design scheme of dual-link DVI, the key technology of the system, and the fabrication of hardware circuit board. The logic realization of codec algorithm and the whole debugging analysis of the system. The maximum pixel clock of the system can reach 330 MHz.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN919.81

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 黎寶峰;嵌入式DSP處理器的設(shè)計與驗證[D];湖南大學(xué);2003年

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本文編號：2326531