【摘要】：脈沖壓縮技術被廣泛的應用在現(xiàn)代雷達系統(tǒng)中,可以同時確保雷達的作用距離以及距離分辨力。而當今雷達已由模擬化轉向數(shù)字化,大大提升了雷達信號處理器的處理速度以及可靠性等方面。目前對于脈沖壓縮處理的實現(xiàn)方法有FPGA,DSP和ASIC。但由于采用DSP和FPGA來實現(xiàn)時,其不但成本較高,并且難以滿足現(xiàn)代雷達信號處理的實時性要求。隨著當代集成電路的發(fā)展,單個芯片的處理能力得到了提升,因而采用ASIC的實現(xiàn)方式可以滿足雷達信號處理的實時性,同時易于批量化的生產(chǎn)可以降低成本。因此,采用ASIC的實現(xiàn)方式是有必要的。本文基于雷達信號處理的理論知識,主要研究了脈沖壓縮技術的ASIC實現(xiàn)方式。首先對雷達信號以及脈沖壓縮的算法進行了研究,并確定采用頻域的處理方法;其次根據(jù)設計目標,設計了基于SDF結構的32~4096點可變點流水線型FFT處理器的硬件電路結構,同時對相關電路進行了優(yōu)化,并且基于上述FFT處理器的結構提出了雙輸入模式的FFT處理器結構;然后提出了可配置的雙路脈沖壓縮的方法,此方法增加了應用的靈活性以及減小了面積的開銷;最后完成了這兩部分的ASIC前端設計以及在功能和時序上的驗證工作。本論文采用Matlab搭建驗證平臺,分別進行了FFT處理器的功能驗證以及脈沖壓縮電路的功能驗證,同時對其結果進行了誤差分析,結果顯示FFT處理器的相對誤差僅為10-5左右,并且脈沖壓縮電路的功能正確。對于上述的設計,同時采用綜合工具Design Compiler#174;,在SMIC.13的標準工藝庫下,完成了脈沖壓縮電路的邏輯綜合,采用Formality#174;進行形式驗證,并且通過PrimeTime#174;對其網(wǎng)表進行了時序分析。
[Abstract]:Pulse compression technology is widely used in modern radar systems, which can ensure the range and range resolution of radar simultaneously. Today, radar has changed from analog to digital, which greatly improves the processing speed and reliability of radar signal processor. At present, the methods of pulse compression are FPGA,DSP and ASIC.. However, when DSP and FPGA are used to realize it, it is not only costly, but also difficult to meet the real-time requirement of modern radar signal processing. With the development of modern integrated circuits, the processing capability of a single chip has been improved. Therefore, the implementation of ASIC can meet the real-time performance of radar signal processing, and easy batch production can reduce the cost. Therefore, it is necessary to implement ASIC. Based on the theoretical knowledge of radar signal processing, this paper mainly studies the ASIC implementation of pulse compression technology. Firstly, the algorithms of radar signal and pulse compression are studied, and the frequency domain processing method is determined. Secondly, according to the design goal, the hardware circuit structure of the 32 / 4096 point variable point pipelined FFT processor based on SDF structure is designed, and the related circuits are optimized. Based on the structure of the FFT processor, a dual-input mode FFT processor architecture is proposed. Then, a configurable dual-channel pulse compression method is proposed, which increases the flexibility of the application and reduces the area overhead. Finally, the design of the ASIC front-end and the verification of the function and timing of the two parts are completed. In this paper, Matlab is used to build the verification platform, the function verification of FFT processor and the function verification of pulse compression circuit are carried out, and the error analysis of the result shows that the relative error of FFT processor is only about 10-5. And the function of pulse compression circuit is correct. For the above design, the logic synthesis of the pulse compression circuit is completed by using the synthesis tool Design Compiler#174;, under the standard process library of SMIC.13. The logic synthesis of the pulse compression circuit is verified by Formality#174; and verified by PrimeTime#174;. The network table is analyzed in time series.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN957.51

【參考文獻】

相關碩士學位論文 前1條

1 湯海華;雷達信號處理脈沖壓縮的設計與實現(xiàn)[D];西安電子科技大學;2014年

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本文編號：2299090