數(shù)字對講機測試技術(shù)及FPGA實現(xiàn)
發(fā)布時間：2018-10-09 16:29
【摘要】：數(shù)字對講機取代模擬對講機,并以其符合現(xiàn)有專用無線通信環(huán)境工作需要的多項功能廣泛應(yīng)用于單位的調(diào)度、指揮、組呼等方面,包括實現(xiàn)點對點或一點對多點的定向通信及完成短消息、文本信息與數(shù)據(jù)傳輸通信等功能。而對講機行業(yè)各個環(huán)節(jié)的發(fā)展,包括研發(fā)、測試、生產(chǎn)等,均會對整個行業(yè)的發(fā)展產(chǎn)生舉足輕重的作用。研究基于硬件的對講機測試,有利于無線電相關(guān)業(yè)務(wù)的順利進行,同時對于對講機產(chǎn)品的研發(fā)技術(shù)、質(zhì)量控制、大規(guī)模生產(chǎn)具有重大意義。本課題來源于基于DMR(Digital Private Mobile Radio)/DPMR(Digital Mobile Radio)/PDT(Police Digital Trunking)協(xié)議的數(shù)字對講機測試系統(tǒng)設(shè)計。DMR系統(tǒng)協(xié)議是由歐洲電信標(biāo)準(zhǔn)協(xié)會(ETSI)制定的開放性的數(shù)字對講機標(biāo)準(zhǔn);DPMR是由ETSI制定的低成本數(shù)字對講機標(biāo)準(zhǔn);PDT是結(jié)合國家公安無線指揮調(diào)度實際通信需求推出的數(shù)字專業(yè)無線通信技術(shù)新標(biāo)準(zhǔn)。本論文在對講機相關(guān)協(xié)議標(biāo)準(zhǔn)研究的基礎(chǔ)上,掌握信號生成技術(shù),運用FPGA硬件開發(fā)技能,研究一套基于FPGA的對講機測試系統(tǒng)。本文所講到的數(shù)字對講機測試系統(tǒng)可分為低頻板及編解碼調(diào)制電路板(簡稱數(shù)字板)兩大模塊,低頻板主要實現(xiàn)人機交互、A/D及D/A轉(zhuǎn)換等功能,數(shù)字板的功能為按照協(xié)議規(guī)定進行測試系統(tǒng)數(shù)字信號處理的相關(guān)工作,包括編解碼及調(diào)制解調(diào)等。本論文著重研究基于DPMR相關(guān)協(xié)議的數(shù)字對講機測試系統(tǒng)的數(shù)字板部分的實現(xiàn)。本文首先介紹了DPMR系統(tǒng)協(xié)議,包括協(xié)議分層結(jié)構(gòu)、幀結(jié)構(gòu)、調(diào)制方式及各個幀的構(gòu)造過程。其次,初步介紹了測試系統(tǒng)整體框架結(jié)構(gòu)及信號生成技術(shù)。最后,文中描述了系統(tǒng)所涉及的接口設(shè)計,接口分為與低頻板之間通信的外部接口及數(shù)字板自身的內(nèi)部接口兩大類,外部接口包括指令解析、雙向口、A/D及D/A接口,內(nèi)部接口主要為FIFO及雙口RAM。接口部分的合理高效設(shè)計及實現(xiàn)是各功能模塊正確有序工作的前提條件,根據(jù)相關(guān)標(biāo)準(zhǔn)及項目實際需要,文中提出了數(shù)字板系統(tǒng)工作的整個流程,研究了各接口在本設(shè)計中的工作時序,同時給出了Verilog HDL設(shè)計關(guān)鍵語句、原理框圖及基于Modelsim的仿真結(jié)果。本設(shè)計基于Altera公司的FPGA進行板級驗證及調(diào)試,通過Quartus II開發(fā)環(huán)境的SignalTap來觀察結(jié)果,目前該系統(tǒng)已初步完成板級驗證及聯(lián)調(diào)工作。文中詳細介紹了從部分到整體聯(lián)調(diào)的整個過程,并給出了實現(xiàn)結(jié)果,同時闡釋了將SignalTap所得數(shù)據(jù)提取出來在Matlab中進行仿真的情況。由于三種協(xié)議在很大程度上具有互聯(lián)互通性,因此,文中所研究的成果為本項目的DMR及PDT測試系統(tǒng)的實現(xiàn)奠定了基礎(chǔ)。
[Abstract]:Digital walkie-talkies replace analog walkie-talkies, and they are widely used in scheduling, command, group calling and other aspects of units, with many functions that meet the needs of the existing dedicated wireless communication environment. It includes the realization of point-to-point or point-to-multipoint directional communication, the completion of short message, the communication between text information and data transmission, and so on. The development of interphone industry, including R & D, testing and production, will play an important role in the development of the whole industry. The study of hardware based interphone testing is beneficial to the smooth progress of radio related services, and is of great significance to the R & D technology, quality control and mass production of interphone products. This topic comes from the design of digital walkie-talkie testing system based on DMR (Digital Private Mobile Radio) / DPMR (Digital Mobile Radio) / PDT (Police Digital Trunking) protocol. DMR system protocol is an open digital interphone standard developed by (ETSI) of European Telecommunication Standards Association. DPMR is a low-cost digital interphone standard developed by ETSI. Digital Interphone Standard (PDT) is a new standard of digital professional wireless communication technology, which is based on the actual communication requirement of national police wireless command and dispatch. Based on the research of interphone protocol standard, this paper grasps the signal generation technology, uses FPGA hardware development skill, studies a set of interphone testing system based on FPGA. The digital interphone testing system mentioned in this paper can be divided into two modules: low frequency board and codec modulation circuit board. The low frequency board mainly realizes the functions of man-machine interaction, such as A / D and D / A conversion. The function of digital board is to deal with digital signal of test system according to protocol, including coding and decoding, modulation and demodulation, etc. This paper focuses on the implementation of digital interphone testing system based on DPMR protocol. This paper first introduces the DPMR system protocol, including the protocol hierarchical structure, frame structure, modulation mode and the construction process of each frame. Secondly, the whole frame structure and signal generation technology of the test system are introduced. Finally, the interface design involved in the system is described. The interface is divided into two categories: the external interface which communicates with the low frequency board and the internal interface of the digital board itself. The external interface includes instruction parsing, bidirectional interface A / D and D / A interface. The internal interface is mainly FIFO and dual-port RAM.. The reasonable and efficient design and realization of the interface part is the precondition for each functional module to work correctly and orderly. According to the relevant standards and the actual needs of the project, the whole process of the work of the digital board system is put forward in this paper. The working sequence of each interface in this design is studied, and the key sentences, schematic block diagrams and simulation results based on Modelsim are given. This design is based on the FPGA of Altera Company for board level verification and debugging. The results are observed by SignalTap in the Quartus II development environment. At present, the system has preliminarily completed the board level verification and joint adjustment work. In this paper, the whole process from part to whole is introduced in detail, and the implementation results are given, and the simulation of extracting the data from SignalTap in Matlab is explained at the same time. Because the three protocols are interconnected to a large extent, the research results in this paper have laid a foundation for the implementation of the DMR and PDT test systems in this project.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN929.54
本文編號：2259997
[Abstract]:Digital walkie-talkies replace analog walkie-talkies, and they are widely used in scheduling, command, group calling and other aspects of units, with many functions that meet the needs of the existing dedicated wireless communication environment. It includes the realization of point-to-point or point-to-multipoint directional communication, the completion of short message, the communication between text information and data transmission, and so on. The development of interphone industry, including R & D, testing and production, will play an important role in the development of the whole industry. The study of hardware based interphone testing is beneficial to the smooth progress of radio related services, and is of great significance to the R & D technology, quality control and mass production of interphone products. This topic comes from the design of digital walkie-talkie testing system based on DMR (Digital Private Mobile Radio) / DPMR (Digital Mobile Radio) / PDT (Police Digital Trunking) protocol. DMR system protocol is an open digital interphone standard developed by (ETSI) of European Telecommunication Standards Association. DPMR is a low-cost digital interphone standard developed by ETSI. Digital Interphone Standard (PDT) is a new standard of digital professional wireless communication technology, which is based on the actual communication requirement of national police wireless command and dispatch. Based on the research of interphone protocol standard, this paper grasps the signal generation technology, uses FPGA hardware development skill, studies a set of interphone testing system based on FPGA. The digital interphone testing system mentioned in this paper can be divided into two modules: low frequency board and codec modulation circuit board. The low frequency board mainly realizes the functions of man-machine interaction, such as A / D and D / A conversion. The function of digital board is to deal with digital signal of test system according to protocol, including coding and decoding, modulation and demodulation, etc. This paper focuses on the implementation of digital interphone testing system based on DPMR protocol. This paper first introduces the DPMR system protocol, including the protocol hierarchical structure, frame structure, modulation mode and the construction process of each frame. Secondly, the whole frame structure and signal generation technology of the test system are introduced. Finally, the interface design involved in the system is described. The interface is divided into two categories: the external interface which communicates with the low frequency board and the internal interface of the digital board itself. The external interface includes instruction parsing, bidirectional interface A / D and D / A interface. The internal interface is mainly FIFO and dual-port RAM.. The reasonable and efficient design and realization of the interface part is the precondition for each functional module to work correctly and orderly. According to the relevant standards and the actual needs of the project, the whole process of the work of the digital board system is put forward in this paper. The working sequence of each interface in this design is studied, and the key sentences, schematic block diagrams and simulation results based on Modelsim are given. This design is based on the FPGA of Altera Company for board level verification and debugging. The results are observed by SignalTap in the Quartus II development environment. At present, the system has preliminarily completed the board level verification and joint adjustment work. In this paper, the whole process from part to whole is introduced in detail, and the implementation results are given, and the simulation of extracting the data from SignalTap in Matlab is explained at the same time. Because the three protocols are interconnected to a large extent, the research results in this paper have laid a foundation for the implementation of the DMR and PDT test systems in this project.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN929.54
【參考文獻】
相關(guān)碩士學(xué)位論文 前2條
1 薛鴻媛;數(shù)字無中心系統(tǒng)數(shù)據(jù)鏈路層的研究與應(yīng)用[D];北京化工大學(xué);2009年
2 樊磊;DPMR數(shù)字對講機射頻一致性指標(biāo)測試研究及自動化測試系統(tǒng)開發(fā)[D];北京郵電大學(xué);2013年
，本文編號：2259997
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