【摘要】：隨著FPGA技術(shù)的發(fā)展,其應(yīng)用領(lǐng)域也在不斷擴(kuò)大�？蒲泄ぷ髡邔PGA用來處理雷達(dá)信號,由于雷達(dá)信號數(shù)據(jù)量大并且要求對信號處理實時完成,傳統(tǒng)的DSP處理器已很難滿足要求。由于FPGA采用并行工作方式,易于實現(xiàn)流水線工作,將逐漸取代DSP在雷達(dá)信號處理領(lǐng)域的主導(dǎo)地位。本文對分布式雷達(dá)控制器及目標(biāo)信息預(yù)處理進(jìn)行研究,完成以下工作:1.介紹了數(shù)字信號邊沿時間與帶寬的關(guān)系,比較詳細(xì)的分析了各類影響信號完整性(SI)的因素,包括傳輸線理論、信號反射、串?dāng)_、差分互連,以及阻抗匹配、走線拓?fù)浣Y(jié)構(gòu)等相關(guān)理論。2.完成了分布式雷達(dá)控制及信號預(yù)處理硬件的設(shè)計實現(xiàn),包括系統(tǒng)方案的確定以及關(guān)鍵器件的選型,系統(tǒng)原理圖包括UART串口電路模塊、數(shù)據(jù)采樣電路模塊、差分驅(qū)動電路模塊,分布式雷達(dá)目標(biāo)信息接收電路模塊等,以及PCB設(shè)計、PCB制作和關(guān)鍵信號的信號完整性仿真。3.完成了分布式雷達(dá)目標(biāo)信息預(yù)處理的關(guān)鍵模塊實現(xiàn),如CORDIC求正余弦模塊,單精度浮點加法運算、單精度浮點乘法運算、定點數(shù)和浮點數(shù)的互相轉(zhuǎn)換。最后對上述基本模塊完成了時序仿真,并與MATLAB仿真結(jié)果進(jìn)行對比達(dá)到預(yù)期精度。4.本文對接收到的目標(biāo)信息進(jìn)行預(yù)處理,從雷達(dá)坐標(biāo)系轉(zhuǎn)換到陣列坐標(biāo)系中,通過前面的各基礎(chǔ)模塊的組合實現(xiàn)陣列坐標(biāo)系目標(biāo)的距離、方位角、俯仰角等,給出的各模塊的仿真結(jié)果及分析,并與MATLAB計算出的結(jié)果進(jìn)行對比達(dá)到預(yù)期精度。
[Abstract]:With the development of FPGA technology, its application field is also expanding. Researchers use FPGA to process radar signals. Because of the large amount of radar signal data and the requirement of real-time signal processing, the traditional DSP processor has been difficult to meet the requirements. Because FPGA adopts parallel working mode, it is easy to realize pipeline operation, which will gradually replace the leading position of DSP in radar signal processing field. In this paper, the distributed radar controller and target information preprocessing are studied, and the following work is accomplished: 1. This paper introduces the relationship between digital signal edge time and bandwidth, and analyzes in detail various factors affecting signal integrity (SI), including transmission line theory, signal reflection, crosstalk, differential interconnection, and impedance matching. Line topology and other related theories. 2. The design and implementation of distributed radar control and signal preprocessing hardware are completed, including the determination of system scheme and the selection of key devices. The system schematic diagram includes UART serial port circuit module, data sampling circuit module, differential drive circuit module. Distributed radar target information receiving circuit module, PCB design, PCB fabrication and signal integrity simulation. 3. The key modules of distributed radar target information preprocessing are completed, such as CORDIC sinusoidal module, single precision floating-point addition operation, single-precision floating-point multiplication operation, and the conversion between fixed point number and floating-point number. Finally, the timing simulation of the above basic modules is completed, and compared with the simulation results of MATLAB, the expected accuracy. 4. 4. In this paper, we preprocess the received target information, transform from radar coordinate system to array coordinate system, realize the distance, azimuth and pitch angle of array coordinate system by the combination of each basic module in front. The simulation results and analysis of each module are given, and compared with the results calculated by MATLAB, the expected accuracy is achieved.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN957.51

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本文編號：2254942