基于CMMB標(biāo)準(zhǔn)的LDPC算法研究及電路實(shí)現(xiàn)
發(fā)布時(shí)間：2018-10-05 18:12
【摘要】：近年來移動終端更新?lián)Q代的速度越來越快,這就對各個商家設(shè)備的性能要求越來越高。為了保證通信系統(tǒng)中信息的可靠傳輸,糾錯編碼是不可或缺的組成部分,在實(shí)際應(yīng)用中LDPC碼是眾多糾錯碼中性能最佳的糾錯碼。21世紀(jì)初,國家廣電總局提出我國移動多媒體規(guī)范CMMB(China Mobile Multimedia Broadcasting)。為了推廣我國自主科研的成果,在全國范圍內(nèi)掀起了研究的熱潮,此規(guī)范的前向糾錯部分是LDPC碼作為內(nèi)碼來完成的。本文不僅完成了LDPC譯碼算法的研究,同時(shí)對譯碼器進(jìn)行電路實(shí)現(xiàn)和FPGA驗(yàn)證,在此基礎(chǔ)上完成邏輯綜合及布局布線的工作。本文首先對比分析了基本的譯碼算法,然后得到了性能更優(yōu)的LDPC譯碼算法。一種是基于最小和算法改進(jìn)的最小次小和算法,該算法簡化了和積算法的復(fù)雜度,譯碼性能比同樣簡化處理的最小和算法更好;另一種是改進(jìn)的分層譯碼算法,該算法克服了傳統(tǒng)分層譯碼可靠度不均勻的缺陷,在相同誤比特率條件下,性能提高了近0.5dB。本文在硬件實(shí)現(xiàn)過程中,分析了算法到硬件實(shí)現(xiàn)的映射過程,并充分考慮到面積、速率和功耗等各方面的權(quán)衡。分層譯碼算法實(shí)現(xiàn)時(shí),一個分層中每一列的列重不能超過1。為了滿足這一限制條件且實(shí)現(xiàn)最大并行度,需要對校驗(yàn)矩陣進(jìn)行等價(jià)轉(zhuǎn)換。面積方面,對后驗(yàn)概率存儲、校驗(yàn)信息存儲以及校驗(yàn)節(jié)點(diǎn)運(yùn)算單元進(jìn)行改進(jìn)。首先,根據(jù)變換后校驗(yàn)矩陣的循環(huán)特點(diǎn),簡化了譯碼過程中后驗(yàn)信息的讀寫操作;其次,對校驗(yàn)信息進(jìn)行壓縮存儲;最后,校驗(yàn)節(jié)點(diǎn)運(yùn)算單元中采用占用面積小的基于指針的求最小次小值方法,并且改變了乘系數(shù)模塊的運(yùn)算順序和運(yùn)算過程,這樣減少了乘系數(shù)模塊的個數(shù),提高了運(yùn)算精度。速率方面,采用部分并行結(jié)構(gòu),并且對后驗(yàn)存儲采用乒乓操作來提升速率。本文最后用VCS平臺自行構(gòu)建測試環(huán)境,充分保證了譯碼器功能的正確性,進(jìn)而在Xilinx的VIRTEX-5型號FPGA上進(jìn)行原型驗(yàn)證。該設(shè)計(jì)吞吐率為20Mbps,滿足CMMB標(biāo)準(zhǔn)16Mbps的要求。后面進(jìn)行的邏輯綜合、布局布線工作保證了時(shí)序收斂。
[Abstract]:In recent years, the speed of upgrading mobile terminals is getting faster and faster. In order to ensure the reliable transmission of information in communication system, error-correcting coding is an indispensable part. In practical application, LDPC code is the best error-correcting code in many error-correcting codes. The State Administration of Radio, Film and Television proposes the Mobile Multimedia Standard CMMB (China Mobile Multimedia Broadcasting). In order to promote the achievements of independent scientific research in our country, there has been a nationwide upsurge of research. The forward error correction part of this standard is completed by LDPC code as internal code. In this paper, not only the research of LDPC decoding algorithm is completed, but also the circuit implementation and FPGA verification of the decoder are carried out. On this basis, logic synthesis and layout and routing are completed. In this paper, the basic decoding algorithms are compared and analyzed firstly, and then the LDPC decoding algorithm with better performance is obtained. One is an improved minimum sum algorithm based on the minimum sum algorithm, which simplifies the complexity of the sum product algorithm, and the decoding performance is better than the minimum sum algorithm, and the other is the improved hierarchical decoding algorithm. The algorithm overcomes the disadvantage of uneven reliability of traditional layered decoding, and improves performance by nearly 0.5 dB under the condition of the same bit error rate (BER). In the process of hardware implementation, the mapping process of algorithm to hardware implementation is analyzed, and the tradeoffs of area, speed and power consumption are fully considered. When the hierarchical decoding algorithm is implemented, the column weight of each column in a layer cannot exceed 1. In order to satisfy this restriction condition and realize the maximum parallelism, it is necessary to transform the check matrix equivalent. In area, the storage of posteriori probability, the storage of checkout information and the operation unit of check node are improved. Firstly, according to the cyclic characteristics of the transformed check matrix, the reading and writing operation of the posteriori information in the decoding process is simplified; secondly, the check information is compressed and stored; finally, In the operation unit of check node, the method of finding minimum value based on pointer with small occupation area is adopted, and the operation sequence and process of multiplication coefficient module are changed, which reduces the number of multiplication coefficient modules and improves the operation precision. In the aspect of rate, partial parallel structure is adopted, and ping-pong operation is used to speed up the posteriori storage. Finally, the test environment is built on VCS platform, which fully ensures the correctness of the decoder function, and then the prototype verification is carried out on the VIRTEX-5 FPGA of Xilinx. The designed throughput is 20 Mbpss, which meets the requirements of CMMB standard 16Mbps. After the logic synthesis, layout and routing to ensure the timing convergence.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN911.22
本文編號：2254372
[Abstract]:In recent years, the speed of upgrading mobile terminals is getting faster and faster. In order to ensure the reliable transmission of information in communication system, error-correcting coding is an indispensable part. In practical application, LDPC code is the best error-correcting code in many error-correcting codes. The State Administration of Radio, Film and Television proposes the Mobile Multimedia Standard CMMB (China Mobile Multimedia Broadcasting). In order to promote the achievements of independent scientific research in our country, there has been a nationwide upsurge of research. The forward error correction part of this standard is completed by LDPC code as internal code. In this paper, not only the research of LDPC decoding algorithm is completed, but also the circuit implementation and FPGA verification of the decoder are carried out. On this basis, logic synthesis and layout and routing are completed. In this paper, the basic decoding algorithms are compared and analyzed firstly, and then the LDPC decoding algorithm with better performance is obtained. One is an improved minimum sum algorithm based on the minimum sum algorithm, which simplifies the complexity of the sum product algorithm, and the decoding performance is better than the minimum sum algorithm, and the other is the improved hierarchical decoding algorithm. The algorithm overcomes the disadvantage of uneven reliability of traditional layered decoding, and improves performance by nearly 0.5 dB under the condition of the same bit error rate (BER). In the process of hardware implementation, the mapping process of algorithm to hardware implementation is analyzed, and the tradeoffs of area, speed and power consumption are fully considered. When the hierarchical decoding algorithm is implemented, the column weight of each column in a layer cannot exceed 1. In order to satisfy this restriction condition and realize the maximum parallelism, it is necessary to transform the check matrix equivalent. In area, the storage of posteriori probability, the storage of checkout information and the operation unit of check node are improved. Firstly, according to the cyclic characteristics of the transformed check matrix, the reading and writing operation of the posteriori information in the decoding process is simplified; secondly, the check information is compressed and stored; finally, In the operation unit of check node, the method of finding minimum value based on pointer with small occupation area is adopted, and the operation sequence and process of multiplication coefficient module are changed, which reduces the number of multiplication coefficient modules and improves the operation precision. In the aspect of rate, partial parallel structure is adopted, and ping-pong operation is used to speed up the posteriori storage. Finally, the test environment is built on VCS platform, which fully ensures the correctness of the decoder function, and then the prototype verification is carried out on the VIRTEX-5 FPGA of Xilinx. The designed throughput is 20 Mbpss, which meets the requirements of CMMB standard 16Mbps. After the logic synthesis, layout and routing to ensure the timing convergence.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN911.22
【參考文獻(xiàn)】
相關(guān)期刊論文 前1條
1 朱慶;吳樂南;;低復(fù)雜度校驗(yàn)節(jié)點(diǎn)調(diào)度的LDPC串行譯碼算法[J];信號處理;2013年05期
相關(guān)碩士學(xué)位論文 前1條
1 程飛;CMMB物理層關(guān)鍵技術(shù)研究與改進(jìn)[D];北京郵電大學(xué);2009年
，本文編號：2254372
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