高速光通信系統(tǒng)接收機(jī)模擬前端電路設(shè)計(jì)
[Abstract]:The advent of the data age has put forward higher requirements for data storage, processing and transmission. With the reduction of unit storage cost and the improvement of processor performance, signal transmission has become the bottleneck of big data era. In recent years, optical communication has been recognized by the government, enterprises and research institutions for its excellent performance, showing great potential and development momentum. At present, high-integration, low-power, high-speed optical communication receiver has become a research hotspot. This paper designs an analog front-end circuit which can be used in high-speed optical communication receiver around chip area, bandwidth, noise, power consumption and so on. The main work of this thesis is as follows: firstly, the general architecture of optical communication receiver is introduced. The influence of important parameters on the random sequence is studied, which provides a theoretical basis for the subsequent design. Secondly, the different main amplifier structures are compared, the limiting amplifier is selected as the main amplifier, and the common limiting amplifier structure is introduced. The inductance free design is realized by using the interstage negative feedback structure. The chip area is greatly reduced, and the stability of the system is analyzed by using the zero pole model. The elimination of DC offset on chip is analyzed and deduced. In view of the large DC misalignment in 65nm, an error amplifier is added to the feedback loop, and a good DC offset cancellation is realized. The chip area of the circuit is 0.11mm ~ 2. The test results show that the differential voltage gain of the limiting amplifier is 37 dB / 3dB and the bandwidth is 16.5 GHz. In the frequency range up to 26.5GHz, Sddll and Sdd22 are less than -16 dB and -9 dB, respectively. Except for the output drive circuit used in the test, the whole chip consumes 50mA current at 1.2 V power supply voltage. Finally, the common transresistance amplifier structure is introduced, the advantages and disadvantages of each structure are compared, the feedback structure is selected based on the common grid circuit, and the noise, bandwidth and power consumption are analyzed and optimized in detail. The simulation results show that the gain of the transresistance amplifier is 48dB 惟, the bandwidth is 28GHz, and the input equivalent integral noise of 3.75u Agna S11 is less than -10dB in 31.5GHz. The transresistance amplifier consumes 10.8mA current at 1.2 V supply voltage. After cascading the transresistance amplifier and the limiting amplifier, the analogue front-end circuit has a -3dB bandwidth of 18.8 GHz and a gain of 88dB 惟.
【學(xué)位授予單位】:復(fù)旦大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2014
【分類號(hào)】:TN929.1
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