【摘要】：針對(duì)現(xiàn)代微處理器和片上系統(tǒng)中時(shí)鐘分布的要求,本文對(duì)現(xiàn)有的數(shù)字延遲鎖相環(huán)的實(shí)現(xiàn)種類進(jìn)行了總結(jié),根據(jù)延遲鎖相環(huán)鎖相速度、面積、功耗等因素的平衡,重點(diǎn)對(duì)逐次逼近寄存器式延遲鎖相環(huán)(Successive Approximation Register controlled Delay-Locked Loop,SAR DLL)進(jìn)行了研究。在可變逐次逼近寄存器式延遲鎖相環(huán)的基礎(chǔ)上進(jìn)行了改進(jìn),提出了移位-可變逐次逼近寄存器式延遲鎖相環(huán)。本文所做的主要工作如下:1、在可變逐次逼近寄存器式延遲鎖相環(huán)的邏輯控制模塊中增加移位控制模塊,即在傳統(tǒng)的二元搜索算法執(zhí)行前,先運(yùn)行二倍搜索算法,這樣就可以將傳統(tǒng)逐次逼近寄存器式延遲鎖相環(huán)中存在的諧波鎖定問(wèn)題避免;2、在移位控制模塊的二倍搜索執(zhí)行完成之后,實(shí)現(xiàn)對(duì)應(yīng)有效控制字位數(shù)逐次逼近寄存器的二元搜索;3、增加的死鎖重啟控制模塊克服了傳統(tǒng)逐次逼近寄存器式延遲鎖相環(huán)只能鎖定一次的缺點(diǎn)。當(dāng)延遲鎖相環(huán)第一次進(jìn)入鎖相狀態(tài)后,由于環(huán)境因素影響跳變到失鎖狀態(tài)后,延遲鎖相環(huán)可以再次重新啟動(dòng)鎖相過(guò)程,使延遲鎖相環(huán)再次進(jìn)入鎖相狀態(tài)。通過(guò)對(duì)移位-可變逐次逼近寄存器式延遲鎖相環(huán)進(jìn)行前端設(shè)計(jì)與仿真,仿真結(jié)果證明了改進(jìn)思路的正確性。當(dāng)控制字有效位數(shù)為3時(shí),S-VSAR算法最長(zhǎng)鎖定時(shí)間比VSAR算法最長(zhǎng)鎖定時(shí)間減少了11.1%;當(dāng)控制字有效位數(shù)為12時(shí),S-VSAR算法最長(zhǎng)鎖定時(shí)間比VSAR算法最長(zhǎng)鎖定時(shí)間減少了75.9%。
[Abstract]:According to the requirements of clock distribution in modern microprocessor and on-chip system, this paper summarizes the existing types of digital delay PLL, according to the balance of speed, area, power consumption and other factors of DPLL. Emphasis is placed on the study of successive approximation register type delay phase locked loop (Successive Approximation Register controlled Delay-Locked Loop,SAR DLL). On the basis of variable successive approximation register type delay phase-locked loop, a shift variable successive approximation register type delay phase locked loop is proposed. The main work of this paper is as follows: 1. The shift control module is added to the logic control module of variable successive approximation register type delay phase-locked loop, that is, the double search algorithm is run before the traditional binary search algorithm is executed. In this way, the harmonic locking problem in the traditional successive approximation register type delay phase locked loop can be avoided, and after the double search of the shift control module is completed, The binary search of successive approximation register corresponding to the number of word bits is realized. The added deadlock restart control module overcomes the shortcoming that the traditional successive approximation register type delay phase locked loop can only be locked once. After the delay PLL enters the phase locked state for the first time, the delay-locked loop can restart the phase lock process again because of the influence of environmental factors, so that the delay-phase locked loop can enter the phase-locked state again. Through the front-end design and simulation of shift-variable successive approximation register type delay PLL, the simulation results show that the improved idea is correct. When the significant number of control words is 3, the longest locking time of S-VSAR algorithm is 11.1 less than that of VSAR algorithm, and the longest locking time of S-VSAR algorithm is 75.9 less than that of VSAR algorithm when the effective number of control words is 12:00.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.8

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本文編號(hào)：2227220