MELP基音檢測算法FPGA實(shí)現(xiàn)研究
發(fā)布時間：2018-08-30 08:33
【摘要】：低速率語音編碼技術(shù)一直是語音通信領(lǐng)域的一個重要發(fā)展方向和研究熱點(diǎn)�；旌霞罹�性預(yù)測編碼(Mixed Excitation Linear Prediction,MELP)算法已被用作美國聯(lián)邦政府的標(biāo)準(zhǔn)算法,并且成為目前應(yīng)用在各種通信系統(tǒng)中的許多低速率乃至極低速率語音編碼算法的主要參考算法,因此在低速率語音編碼領(lǐng)域占有重要的地位。在實(shí)際應(yīng)用中,一種合適的實(shí)現(xiàn)平臺對MELP算法的有效應(yīng)用有著重要的影響。目前,研究者一般都以各種DSP處理器為平臺對MELP算法的實(shí)現(xiàn)進(jìn)行研究。近年來,隨著制造工藝水平的快速發(fā)展,現(xiàn)場可編程門陣列(Field Programmable Gate Array,FPGA)芯片的規(guī)模已發(fā)展到等效于千萬級的ASIC門,為其廣泛應(yīng)用于數(shù)字信號處理領(lǐng)域創(chuàng)造了條件。隨著FPGA在數(shù)字信號處理領(lǐng)域中的應(yīng)用越來越多,基于FPGA平臺的語音通信系統(tǒng)的研究也成為實(shí)際應(yīng)用的需要。MELP編碼算法中,基音周期是需要計(jì)算并編碼傳輸?shù)恼Z音信號的關(guān)鍵特征參數(shù),對算法合成語音的質(zhì)量有著直接的影響。MELP基音檢測算法的作用是提取出語音信號的基音周期,是整個算法中的重要組成部分。MELP基音檢測算法的算法復(fù)雜度較高,因而很難在FPGA平臺上實(shí)現(xiàn)。但由于其在語音編碼算法中的重要性,本文仍將MELP基音檢測算法作為研究對象,對其在FPGA平臺上的實(shí)現(xiàn)進(jìn)行了研究。首先,作為理論基礎(chǔ),本文對MELP算法的編解碼流程進(jìn)行了簡要介紹,并對MELP基音檢測算法的實(shí)現(xiàn)過程進(jìn)行了詳細(xì)的分析。然后,為在FPGA平臺上實(shí)現(xiàn)MELP基音檢測算法,本文對FPGA及其設(shè)計(jì)方法進(jìn)行了研究。最后,本文在MELP基音檢測算法的C定點(diǎn)實(shí)現(xiàn)程序和對算法原理的理解的基礎(chǔ)上,用Verilog HDL設(shè)計(jì)了MELP基音檢測算法的硬件模型,完成了MELP基音檢測算法在FPGA平臺上的實(shí)現(xiàn)。在用Verilog HDL對MELP基音檢測算法進(jìn)行建模時,本文采用了自下而上的設(shè)計(jì)方法。從最低層的加法、乘法等基本運(yùn)算單元開始,到整數(shù)基音周期計(jì)算、分?jǐn)?shù)基音周期計(jì)算等高層功能模塊,分別建立了相應(yīng)的硬件模型。通過層層建模最終完成了MELP基音檢測算法整體的FPGA實(shí)現(xiàn)。并在實(shí)現(xiàn)過程中從處理速度和資源消耗兩個方面分別對各層模型的設(shè)計(jì)進(jìn)行了優(yōu)化。在對本文的實(shí)現(xiàn)結(jié)果進(jìn)行性能分析時,本文通過與Vivado HLS轉(zhuǎn)換相應(yīng)C語言函數(shù)得到的FPGA實(shí)現(xiàn)結(jié)果相比,結(jié)果顯示本文實(shí)現(xiàn)結(jié)果具有良好的面積性能;通過對本文實(shí)現(xiàn)的處理時間和計(jì)算結(jié)果的分析,結(jié)果表明本文的實(shí)現(xiàn)結(jié)果在處理速度和計(jì)算結(jié)果兩個方面也表現(xiàn)良好。
[Abstract]:Low-rate speech coding technology has been an important development direction and research hotspot in the field of speech communication. Hybrid excited Linear Predictive coding (Mixed Excitation Linear Prediction,MELP) algorithm has been used as the standard algorithm of the Federal Government of the United States, and has become the main reference algorithm for many low rate and even very low rate speech coding algorithms used in various communication systems. Therefore, it plays an important role in the field of low rate speech coding. In practical applications, a suitable implementation platform has an important impact on the effective application of MELP algorithm. At present, researchers generally study the implementation of MELP algorithm based on various DSP processors. In recent years, with the rapid development of manufacturing technology, the scale of field programmable gate array (Field Programmable Gate Array,FPGA) chip has developed to equivalent to tens of millions of ASIC gates, which has created conditions for its wide application in the field of digital signal processing. With more and more applications of FPGA in the field of digital signal processing, the research of voice communication system based on FPGA platform has become the need of practical application. Pitch period is the key characteristic parameter of speech signal which needs to be calculated and encoded and transmitted. It has a direct influence on the quality of synthesized speech. The function of MELP pitch detection algorithm is to extract pitch period of speech signal. MELP pitch detection algorithm is an important part of the whole algorithm. The algorithm complexity of MELP pitch detection algorithm is high, so it is difficult to implement on FPGA platform. However, due to its importance in speech coding algorithm, this paper still takes the MELP pitch detection algorithm as the research object, and studies its implementation on the FPGA platform. Firstly, as the theoretical basis, this paper briefly introduces the coding and decoding flow of MELP algorithm, and analyzes the realization process of MELP pitch detection algorithm in detail. Then, in order to realize MELP pitch detection algorithm on FPGA platform, this paper studies FPGA and its design method. Finally, on the basis of the C point realization program of MELP pitch detection algorithm and the understanding of the principle of the algorithm, the hardware model of MELP pitch detection algorithm is designed with Verilog HDL, and the realization of MELP pitch detection algorithm on FPGA platform is completed. In the modeling of MELP pitch detection algorithm with Verilog HDL, the bottom-up design method is adopted in this paper. Starting from the basic operation units of the lowest layer, such as addition and multiplication, to the higher functional modules, such as integer pitch cycle calculation and fractional pitch period calculation, the corresponding hardware models are established respectively. Finally, the whole FPGA implementation of MELP pitch detection algorithm is completed by layer modeling. In the process of implementation, the design of each layer model is optimized from two aspects: processing speed and resource consumption. In the performance analysis of the implementation results of this paper, compared with the FPGA implementation results obtained from the corresponding C language functions converted by Vivado HLS, the results show that the results of this paper have good area performance. Through the analysis of the processing time and the calculation results, the results show that the results of this paper are also good in two aspects: the processing speed and the calculation results.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN912.3
本文編號：2212544
[Abstract]:Low-rate speech coding technology has been an important development direction and research hotspot in the field of speech communication. Hybrid excited Linear Predictive coding (Mixed Excitation Linear Prediction,MELP) algorithm has been used as the standard algorithm of the Federal Government of the United States, and has become the main reference algorithm for many low rate and even very low rate speech coding algorithms used in various communication systems. Therefore, it plays an important role in the field of low rate speech coding. In practical applications, a suitable implementation platform has an important impact on the effective application of MELP algorithm. At present, researchers generally study the implementation of MELP algorithm based on various DSP processors. In recent years, with the rapid development of manufacturing technology, the scale of field programmable gate array (Field Programmable Gate Array,FPGA) chip has developed to equivalent to tens of millions of ASIC gates, which has created conditions for its wide application in the field of digital signal processing. With more and more applications of FPGA in the field of digital signal processing, the research of voice communication system based on FPGA platform has become the need of practical application. Pitch period is the key characteristic parameter of speech signal which needs to be calculated and encoded and transmitted. It has a direct influence on the quality of synthesized speech. The function of MELP pitch detection algorithm is to extract pitch period of speech signal. MELP pitch detection algorithm is an important part of the whole algorithm. The algorithm complexity of MELP pitch detection algorithm is high, so it is difficult to implement on FPGA platform. However, due to its importance in speech coding algorithm, this paper still takes the MELP pitch detection algorithm as the research object, and studies its implementation on the FPGA platform. Firstly, as the theoretical basis, this paper briefly introduces the coding and decoding flow of MELP algorithm, and analyzes the realization process of MELP pitch detection algorithm in detail. Then, in order to realize MELP pitch detection algorithm on FPGA platform, this paper studies FPGA and its design method. Finally, on the basis of the C point realization program of MELP pitch detection algorithm and the understanding of the principle of the algorithm, the hardware model of MELP pitch detection algorithm is designed with Verilog HDL, and the realization of MELP pitch detection algorithm on FPGA platform is completed. In the modeling of MELP pitch detection algorithm with Verilog HDL, the bottom-up design method is adopted in this paper. Starting from the basic operation units of the lowest layer, such as addition and multiplication, to the higher functional modules, such as integer pitch cycle calculation and fractional pitch period calculation, the corresponding hardware models are established respectively. Finally, the whole FPGA implementation of MELP pitch detection algorithm is completed by layer modeling. In the process of implementation, the design of each layer model is optimized from two aspects: processing speed and resource consumption. In the performance analysis of the implementation results of this paper, compared with the FPGA implementation results obtained from the corresponding C language functions converted by Vivado HLS, the results show that the results of this paper have good area performance. Through the analysis of the processing time and the calculation results, the results show that the results of this paper are also good in two aspects: the processing speed and the calculation results.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN912.3
【參考文獻(xiàn)】
相關(guān)期刊論文 前1條
1 郭立;王妙鋒;劉璐;郁理;李琳;;1.6Kb/s類MELP語音壓縮編碼器的FPGA實(shí)現(xiàn)[J];小型微型計(jì)算機(jī)系統(tǒng);2008年08期
，本文編號：2212544
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