【摘要】：現(xiàn)代無線通信技術(shù)飛速發(fā)展,不同的對象有著不同的通信需求,軟件無線電的思想是隨著用戶習(xí)慣和時(shí)代發(fā)展順勢被提出來的。它要求建立一個(gè)統(tǒng)一標(biāo)準(zhǔn)化的平臺(tái),而零中頻結(jié)構(gòu)簡單,AD/DA靠近天線端,不僅是超外差結(jié)構(gòu)的發(fā)展,同時(shí)也是軟件無線電思想的應(yīng)用。零中頻架構(gòu)具有體積小、功耗低、成本低的優(yōu)勢,如今在手機(jī)通信中已經(jīng)被廣泛地應(yīng)用了,很多芯片供應(yīng)商都推出了針對移動(dòng)通信標(biāo)準(zhǔn)的零中頻收發(fā)器；在雷達(dá)應(yīng)用中,多功能相控陣?yán)走_(dá)的通道數(shù)成千上萬,而零中頻架構(gòu)的優(yōu)勢就凸顯出來了。本文就是針對這樣的應(yīng)用背景,研究并設(shè)計(jì)出了基于FMC(FPGA Mezzanine Card)標(biāo)準(zhǔn)的寬帶零中頻收發(fā)前端。 本文主要完成的工作： 1.研究了收發(fā)機(jī)前端主要的結(jié)構(gòu),分析了各自的優(yōu)勢和存在的問題,根據(jù)應(yīng)用背景,選擇了零中頻架構(gòu)。 2.介紹了收發(fā)射頻前端的技術(shù)指標(biāo),提出了總體設(shè)計(jì)方案,根據(jù)性能指標(biāo),選用合適器件,根據(jù)器件的性能參數(shù)對接收機(jī)系統(tǒng)進(jìn)行信道選擇性仿真、增益預(yù)算仿真、輸出信號頻譜仿真。 3.完成寬帶零中頻收發(fā)前端的硬件設(shè)計(jì),包括本振模塊設(shè)計(jì)、正交調(diào)制模塊設(shè)計(jì)、正交解調(diào)模塊設(shè)計(jì)、AD/DA模塊設(shè)計(jì)和核心芯片間的接口設(shè)計(jì)等,闡述了射頻PCB設(shè)計(jì)的要點(diǎn)。 4.對設(shè)計(jì)出來的FMC寬帶零中頻收發(fā)前端板卡進(jìn)行測試,各功能模塊良好工作,測試了其IQ幅相不平衡性。
[Abstract]:With the rapid development of modern wireless communication technology, different objects have different communication requirements. The idea of software radio has been put forward with the development of user habits and times. It requires the establishment of a unified and standardized platform, and the zero if structure is simple AD-DA near the antenna, which is not only the development of the superheterodyne structure, but also the application of the software radio idea. Zero-if architecture has the advantages of small size, low power consumption and low cost. Nowadays, it has been widely used in mobile communication. Many chip providers have introduced zero-if transceiver for mobile communication standard. There are thousands of channels for multi-functional phased array radar, and the advantages of zero intermediate frequency architecture are highlighted. In this paper, we study and design a wideband zero if transceiver front end based on FMC (FPGA Mezzanine Card) standard. The main work of this paper is as follows: 1. The main structure of the transceiver front-end is studied, and their advantages and problems are analyzed. According to the application background, the zero-if architecture is selected. This paper introduces the technical specifications of the transceiver RF front end, and puts forward the overall design scheme. According to the performance index, the appropriate device is selected, and the channel selectivity simulation and gain budget simulation are carried out according to the device performance parameters. Output signal spectrum simulation. 3. Complete the hardware design of wideband zero-if transceiver front end, including local oscillator module design, quadrature modulation module design, quadrature demodulation module design, AD-DA module design and interface design between core chips, etc. The main points of RF PCB design are described. 4. The design of FMC wideband zero-if transceiver front-end card is tested. The function modules work well and its IQ amplitude and phase imbalance is tested.
【學(xué)位授予單位】：南京信息工程大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN92

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