【摘要】：隨著通訊技術(shù)的發(fā)展,并行傳輸方式已經(jīng)難以滿足帶寬和功耗等要求,串行傳輸方式由于傳輸速度快、功耗低和抗干擾能力強(qiáng)等優(yōu)點(diǎn),成為主流的傳輸方式。SERDES接口能夠?qū)崿F(xiàn)并行與串行相互轉(zhuǎn)換的功能,成為主流的傳輸接口。其中,8B/10B SERDES由于具有直流平衡和易于交流耦合等優(yōu)點(diǎn),成為接口電路研究的熱點(diǎn)。本文介紹了SERDES系統(tǒng)架構(gòu)的四種實(shí)現(xiàn)方式,并根據(jù)各自的優(yōu)缺點(diǎn),選定了8B/10B SERDES為研究對(duì)象,詳細(xì)分析與介紹了SERDES系統(tǒng)中的各個(gè)模塊的工作原理,包括并串轉(zhuǎn)換電路、半速率時(shí)鐘選擇電路、占空比1：5的五分頻電路和串并轉(zhuǎn)換電路等。最后按照發(fā)送通道與接收通道對(duì)系統(tǒng)進(jìn)行了Simulink建模。在并行信號(hào)輸入時(shí)鐘頻率為250MHz時(shí),輸出信號(hào)頻率可達(dá)到2.5Gbps。電荷泵鎖相環(huán)(CPPLL)作為8B/10B SERDES中的重要組成部分,為整個(gè)系統(tǒng)提供時(shí)鐘,其性能將直接影響傳輸精度。本文對(duì)電荷泵鎖相環(huán)的各個(gè)組成部分進(jìn)行了理論和非理想因素分析,并給出了本文的電路設(shè)計(jì)與非理想因素解決方法。最后在1.2/2.5V電源電壓下,使用SMIC 65nm CMOS工藝,對(duì)電荷泵鎖相環(huán)進(jìn)行了仿真與分析。由仿真結(jié)果可以得知,在輸入信號(hào)頻率為100MHz時(shí),CPPLL穩(wěn)定輸出2.5GHz時(shí)鐘信號(hào),鎖定時(shí)間僅需0.6us,符合SERDES系統(tǒng)對(duì)CPPLL的性能要求。
[Abstract]:With the development of communication technology, the parallel transmission mode has been difficult to meet the requirements of bandwidth and power consumption. The serial transmission mode has the advantages of high transmission speed, low power consumption and strong anti-interference ability. The main transmission mode. SERDES interface can realize the function of parallel and serial conversion and become the mainstream transmission interface. Among them, 8B / 10B SERDES has the advantages of DC balance and easy AC coupling, so it has become a hotspot in the research of interface circuits. This paper introduces four realization methods of SERDES system architecture, and selects 8B/10B SERDES as the research object according to their advantages and disadvantages. The working principle of each module in SERDES system is analyzed and introduced in detail, including parallel series conversion circuit. Half-rate clock selection circuit, duty cycle 1:5 five-frequency circuit and serial-parallel conversion circuit. Finally, the Simulink model of the system is built according to the transmission channel and the receiving channel. When the input clock frequency of the parallel signal is 250MHz, the output signal frequency can reach 2.5 Gbps. As an important part of 8B/10B SERDES, the charge pump PLL (CPPLL) provides the clock for the whole system, and its performance will directly affect the transmission accuracy. In this paper, the various components of the charge pump phase-locked loop are analyzed theoretically and the non-ideal factors are analyzed, and the circuit design and the solution of the non-ideal factors are given. Finally, the charge pump PLL is simulated and analyzed at 1.2 / 2.5V power supply voltage using SMIC 65nm CMOS process. The simulation results show that the 2.5GHz clock signal is output stably when the input signal frequency is 100MHz, and the locking time is only 0.6 us.This meets the performance requirements of SERDES system for CPPLL.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN911.8

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本文編號(hào)：2182142