本文選題：硅基微型顯示器 + 計(jì)算型存儲器　； 參考：《上海大學(xué)》2014年博士論文

【摘要】：微型顯示器由于體積小、重量輕、功耗低而成為理想便攜式、可穿戴式顯示器的首選。在各類微型顯示器中，以單晶硅為基底的硅基OLED微型顯示器由于其較高的載流子遷移率和成熟的CMOS集成電路設(shè)計(jì)技術(shù)，能夠在硅芯片上集成高密度的有源尋址矩陣、周邊驅(qū)動電路和顯示控制器，可以有效地提高硅基微型顯示器的像素密度、可靠性和穩(wěn)定性。隨著硅基芯片集成度的提高和人們對便攜式設(shè)備較長的電池使用壽命的期望增加，功耗成為硅基微型顯示器芯片設(shè)計(jì)中的一個(gè)相當(dāng)關(guān)鍵的問題。本文圍繞基于最優(yōu)掃描算法的硅基微型顯示器的關(guān)鍵存儲器設(shè)計(jì)技術(shù)，針對存儲器架構(gòu)、低功耗策略等展開了深入的研究，主要研究內(nèi)容包括： 一、針對硅基微型顯示器中圖像處理邏輯與片外幀數(shù)據(jù)存儲器之間的性能差異及片間驅(qū)動大電容引起的高功耗問題，本文提出了高能效的計(jì)算型存儲器結(jié)構(gòu)，該結(jié)構(gòu)將圖像處理邏輯電路與存儲器電路集成到一個(gè)芯片模塊上，以充分利用片內(nèi)存儲器的高帶寬和較小的信號傳輸延遲，不僅提高了圖形處理邏輯的并行性，而且降低了系統(tǒng)功耗和設(shè)計(jì)面積。 二、從CMOS電路功耗模型分析入手，探尋功耗來源及影響因素，分析了各類動態(tài)功耗和靜態(tài)功耗的優(yōu)化技術(shù)的原理，在此基礎(chǔ)上，，針對Flash存儲器特點(diǎn)，提出了Flash存儲器的低功耗設(shè)計(jì)策略，包括（1）采用多種系統(tǒng)模式（工作模式、靜態(tài)模式、深睡眠模式和電源關(guān)斷模式），以形成系統(tǒng)不同的低功耗狀態(tài)；（2）采用異構(gòu)電路設(shè)計(jì)方法，極大縮減了時(shí)鐘反轉(zhuǎn)引起的動態(tài)功耗以及時(shí)鐘等待所需要的靜態(tài)功耗；（3）采用低電源電壓技術(shù)和多閾值電壓技術(shù)，在保證系統(tǒng)高性能的條件下，使系統(tǒng)具有很低的功耗；（4）增設(shè)使能信號，在工作模式下，對非工作狀態(tài)的電路子塊進(jìn)行休眠處理，從而降低了動態(tài)功耗，同時(shí)結(jié)合多閾值電壓技術(shù)，使系統(tǒng)具有極低的靜態(tài)功耗。 三、基于低功耗策略，在架構(gòu)和電路上采用基于柵漏分離電流鏡的靈敏放大器技術(shù)及三環(huán)路控制LDO技術(shù)完成了一款低功耗Flash存儲器電路設(shè)計(jì)。本文提出的基于柵漏分離的電流鏡和高性能動態(tài)比較器，并以此構(gòu)成的靈敏放大器，除保證了較高的讀取精度外，由于具有較低的工作電壓和讀取電流，因而使功耗有明顯的降低。提出的基于三環(huán)路控制的無片外電容型LDO，采用了電容耦合效應(yīng)和自適應(yīng)基準(zhǔn)準(zhǔn)技術(shù)，從而提高了響應(yīng)速度使Flash存儲器有著很快的上電時(shí)間，以快速進(jìn)入工作狀態(tài)，同時(shí)由于其較低的靜態(tài)電流使其功耗較小。上述的關(guān)鍵電路結(jié)構(gòu)，不僅適用于低壓低功耗操作的Flash Memory的需求，而且對其它電路應(yīng)用有著重要的參考價(jià)值。 四、對硅基OLED微型顯示器最優(yōu)掃描系統(tǒng)的設(shè)計(jì)展開了研究，以此作為本文提出的計(jì)算型存儲器結(jié)構(gòu)和基于低功耗設(shè)計(jì)的Flash Memory的重要應(yīng)用和驗(yàn)證平臺。重點(diǎn)討論了顯示優(yōu)化控制器和顯示驅(qū)動器的設(shè)計(jì)、電路實(shí)現(xiàn)，版圖設(shè)計(jì)及驗(yàn)證。由于芯片集成度比較高，本設(shè)計(jì)采用全定制方法和半定制方法相結(jié)合的設(shè)計(jì)方法，對于關(guān)鍵電路采用全定制方法設(shè)計(jì)，非關(guān)鍵電路采用半定制方法設(shè)計(jì)，設(shè)計(jì)層次為邏輯級，輸出為門級網(wǎng)表，最后在系統(tǒng)頂層進(jìn)行布局布線。
[Abstract]:Small displays, light weight and low power consumption have become ideal portable and wearable displays. In various micro displays, silicon based OLED micro displays based on monocrystalline silicon can integrate high density of silicon on silicon chips due to their high carrier mobility and mature CMOS integrated circuit design techniques. The active addressing matrix, the peripheral drive circuit and the display controller can effectively improve the pixel density, reliability and stability of the silicon based micro display. With the improvement of the silicon based chip integration and the increasing expectation of the longer battery life of the portable devices, the power consumption has become one of the design of the silicon based micro display chip. This paper focuses on the key memory design technology of the silicon based micro display based on the optimal scanning algorithm, and has carried out a deep research on the memory architecture and low power strategy. The main research contents include:
First, in view of the performance difference between the image processing logic and the outer frame data memory in the silicon based micro display and the high power consumption caused by the large capacitance of the chip drive, this paper presents a highly efficient computational memory structure which integrates the image processing logic circuit and the memory circuit to a chip module to fully profit. The high bandwidth and smaller signal transmission delay of the chip storage device not only enhance the parallelism of the graphics processing logic, but also reduce the system power consumption and the design area.
Two, from the analysis of the CMOS circuit power model, the power source and the influencing factors are explored, and the principle of the optimization technology of all kinds of dynamic and static power is analyzed. On this basis, the low power design strategy of the Flash memory is proposed for the characteristics of the Flash memory, including (1) using a variety of system modes (working mode, static mode, depth) Sleep mode and power switch mode) to form different low power state of the system; (2) the use of isomeric circuit design method greatly reduces the dynamic power consumption caused by clock reversal and the static power consumption required by the clock waiting; (3) using low power supply voltage technology and multi threshold voltage technology, under the condition of ensuring the high performance of the system, The system has very low power consumption; (4) the power signal is added, and the non working circuit subblock is dormant under the working mode, which reduces the dynamic power consumption and combines the multi threshold voltage technology to make the system very low static power.
Three, based on the low power consumption strategy, a low power Flash memory circuit is designed by using the sensitive amplifier technology based on the gate leakage separation current mirror and the three loop control LDO technology. The current mirror and the high performance dynamic comparator based on the gate leakage separation are proposed, and the sensitive amplifier which is made up of this method is guaranteed. In addition to the higher reading accuracy, the power consumption is significantly reduced because of the low working voltage and reading current. The proposed three loop based non chip capacitive LDO, which uses the capacitive coupling effect and the adaptive datum quasi technology, improves the response speed to make the Flash memory have a very fast power up time, and fast. The key circuit structure mentioned above is not only applicable to the demand of Flash Memory for low voltage and low power operation, but also has important reference value for other circuit applications.
Four, the design of the optimal scanning system for silicon based OLED micro display is studied. As an important application and verification platform for the computational memory structure and Flash Memory based on low power design, the design, circuit implementation, layout design and verification of the display optimization controller and display driver are discussed. The integration degree of chip is high. This design adopts a design method combining full custom method with semi customizing method. The design method is designed with full custom method for key circuits. Semi custom method is used to design non key circuits. The design level is logic level, output is gate level net table, and finally the layout and wiring at the top layer of the system are carried out.
【學(xué)位授予單位】：上海大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2014
【分類號】：TN873;TP333

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相關(guān)期刊論文 前3條

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本文編號：2107598