本文選題：VI-CFAR + EOSVI-CFAR��； 參考：《西安電子科技大學(xué)》2014年碩士論文

【摘要】：雷達(dá)信號處理中恒虛警率(CFAR)處理的目的是為了在目標(biāo)檢測過程中可以保證穩(wěn)定的虛警率。不同的恒虛警率算法在某些環(huán)境中有較好的檢測性能,但是在其余環(huán)境下性能惡化驗證。對多種CFAR算法研究后發(fā)現(xiàn),VI-CFAR在均勻背景,雜波邊緣背景下均有較好的性能,但在多目標(biāo)尤其是前后參考窗均存在干擾時其檢測性能下降嚴(yán)重�；谶@種情況,本文首先提出了一種改進(jìn)的VI-CFAR檢測方法-EOSVI-CFAR,此方法通過改變VI選擇不同恒虛警的判別條件并且引入了有序統(tǒng)計OS-CFAR算法。對EOSVI-CFAR進(jìn)行Matlab建模后,仿真結(jié)果表明,改進(jìn)后的算法有效改善了VI-CFAR的多目標(biāo)環(huán)境下檢測性能下降的問題,同時在均勻環(huán)境,雜波邊緣環(huán)境下仍保持著較好的性能。隨后本文進(jìn)行算法的硬件設(shè)計。根據(jù)要求給出了電路的實現(xiàn)方案,核心的模塊包括:累加求和模塊、乘累加模塊、關(guān)鍵判別函數(shù)模塊、控制模塊、閾值生成模塊、高速插入排序模塊。為了提高處理器的工作頻率,在原有的排序電路基礎(chǔ)上提出了新的實現(xiàn)方案,使用ISE Virtex5綜合后最大時鐘頻率比原版提高了10%,大大增強(qiáng)了處理器的性能。對于排序,累加和,乘累加和結(jié)果使用延遲電路有效的減小了面積消耗。在功能驗證階段,使用MATLAB,Modelsim聯(lián)合仿真,將前者的輸出結(jié)果與后者的輸出結(jié)果進(jìn)行對比分析,結(jié)果一致證明硬件實現(xiàn)正確。使用DC#174;在0.18μm工藝下綜合,面積為760106μm2,最壞情況下時鐘頻率可達(dá)215MHz。第一個數(shù)據(jù)從輸入到結(jié)果輸出需要31個時鐘周期。對RTL和綜合的網(wǎng)表做形式驗證,結(jié)果表明二者一致。最后采用ICC#174;進(jìn)行后端實現(xiàn)。最終布局布線后核的面積為1520233μm2,功耗為67.8mW。
[Abstract]:The purpose of constant false alarm rate (CFAR) processing in radar signal processing is to ensure a stable false alarm rate in the process of target detection. Different CFAR algorithms have better detection performance in some environments, but in others, the performance deterioration is verified. After studying various CFAR algorithms, it is found that VI-CFAR has better performance in homogeneous background and clutter edge background, but the detection performance of VI-CFAR is degraded seriously when there is interference in multiple targets, especially in front and rear reference windows. Based on this situation, an improved VI-CFAR detection method-EOSVI-CFAR is proposed in this paper. By changing VI to select different CFAR criteria, an ordered statistical OS-CFAR algorithm is introduced. After modeling EOSVI-CFAR with Matlab, the simulation results show that the improved algorithm can effectively improve the performance degradation of VI-CFAR in multi-target environment, while maintaining good performance in homogeneous environment and clutter edge environment. Then this paper designs the hardware of the algorithm. According to the requirements, the implementation scheme of the circuit is given. The core modules include: cumulative summation module, multiplicative accumulation module, key discriminant function module, control module, threshold generation module, high speed insertion sorting module. In order to improve the working frequency of the processor, a new scheme is proposed on the basis of the original sort circuit. The maximum clock frequency of ISE Virtex5 synthesis is 10 times higher than that of the original, which greatly enhances the performance of the processor. For sorting, summation, multiplicative summation and results, delay circuits are used to effectively reduce area consumption. In the phase of function verification, the output results of the former are compared with those of the latter by MATLAB Modelsim simulation. The results show that the hardware implementation is correct. DC#174was used in the process of 0.18 渭 m, the area was 760106 渭 m ~ 2, and the clock frequency could reach 215 MHz in the worst case. The first data requires 31 clock cycles from input to output. The results of formal verification of RTL and synthetic network table show that the two are consistent. Finally, ICC #174 is used to implement the back end. The area of the core is 1520233 渭 m ~ 2 and the power consumption is 67.8 MW.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN957.51

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本文編號：2100691