本文選題：DMA控制器 + 實(shí)時成像　； 參考：《南京大學(xué)》2014年碩士論文

【摘要】：Backprojection雷達(dá)成像算法是合成孔徑雷達(dá)成像算法中的一種,該算法能在高分辨率、大前斜視角、低頻以及大孔徑積分角的情況下成像。算法主要包括脈沖預(yù)處理和脈沖反投影兩個部分,其中脈沖反投影部分的運(yùn)算量極大,需要通過使用并行計算的方法來解決這個瓶頸。本文介紹了一款面向?qū)崟r成像算法的多核異構(gòu)處理平臺,并在該平臺上實(shí)現(xiàn)了Backproiection成像多核并行計算系統(tǒng)。在該計算系統(tǒng)的反投影子系統(tǒng)中集成了8個反投影加速核,這些反投影加速核通過脈沖并行的方式實(shí)現(xiàn)了流水并行。為了滿足流水并行對數(shù)據(jù)傳輸需求,本文設(shè)計一款支持并行傳輸?shù)亩喽丝贒MA控制器。該DMA控制器包含1個配置端口,2個數(shù)據(jù)通道和5個設(shè)備端口。DMA控制器只在配置過程中使用AHB總線,數(shù)據(jù)的傳輸采用專用的數(shù)據(jù)通道,源設(shè)備和目的設(shè)備經(jīng)由數(shù)據(jù)通道中FIFO的緩存通過傳輸協(xié)議相連接而實(shí)現(xiàn)數(shù)據(jù)的傳輸,各個數(shù)據(jù)通道之間相互獨(dú)立。在Backproiection成像多核并行計算系統(tǒng)中,該DMA控制器實(shí)現(xiàn)了雙數(shù)據(jù)通道并行傳輸,單個數(shù)據(jù)通道傳輸效率超過97%,整體傳輸效率達(dá)到195%,滿足了計算系統(tǒng)的需求。本文介紹了支持并行傳輸?shù)亩喽丝贒MA控制器的設(shè)計方法。闡述該DMA控制器的總體結(jié)構(gòu)、工作特點(diǎn)、工作原理以及工作流程,并詳細(xì)介紹了該DMA控制器各個子模塊的設(shè)計方法。在設(shè)計完成后,對DMA控制器進(jìn)行了系統(tǒng)級功能驗(yàn)證,驗(yàn)證該DMA控制器功能是否正確。經(jīng)驗(yàn)證,本文設(shè)計的DMA控制器數(shù)據(jù)傳輸正確,符合設(shè)計的要求。目前,該DMA控制器已經(jīng)作為Backproiection成像多核并行計算系統(tǒng)的一部分集成到本文介紹的多核異構(gòu)處理平臺中,并實(shí)現(xiàn)了基于Xillinx V6550T FPGA芯片的實(shí)時成像原型演示系統(tǒng)。
[Abstract]:Backprojection radar imaging algorithm is one of synthetic Aperture Radar (SAR) imaging algorithms. This algorithm can be used to image high resolution, large front angle, low frequency and large aperture integral angle. The algorithm mainly consists of two parts: pulse preprocessing and pulse backprojection, in which the computation of pulse backprojection is very heavy, so it is necessary to solve this bottleneck by using parallel computing method. In this paper, a multi-core heterogeneous processing platform for real-time imaging algorithm is introduced, and a multi-core parallel computing system for Backproiection imaging is implemented on the platform. Eight backprojection accelerating kernels are integrated into the backcast shadow system of the computing system. These backprojection accelerating kernels realize pipeline parallelism by pulse parallelism. In order to meet the requirement of pipelined parallel data transmission, a multi-port DMA controller supporting parallel transmission is designed in this paper. The DMA controller consists of one configuration port, two data channels and five device ports. The source device and the destination device transmit data through the buffer of FIFO in the data channel through the transmission protocol, and each data channel is independent of each other. In the multi-core parallel computing system of Backproection imaging, the DMA controller realizes the dual data channel parallel transmission. The transmission efficiency of a single data channel exceeds 97 and the overall transmission efficiency reaches 195, which meets the needs of the computing system. This paper introduces the design method of multi-port DMA controller which supports parallel transmission. The general structure, working characteristics, working principle and working flow of the DMA controller are described, and the design method of each sub-module of the DMA controller is introduced in detail. After the design is finished, the system-level function of DMA controller is verified to verify whether the DMA controller is correct or not. It is verified that the data transmission of DMA controller designed in this paper is correct and meets the requirements of the design. At present, the DMA controller has been integrated into the multi-core heterogeneous processing platform introduced in this paper as a part of the parallel computing system for backtracking imaging, and a real-time imaging prototype demonstration system based on Xillinx V6550T FPGA chip has been implemented.
【學(xué)位授予單位】：南京大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN958;TP273

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本文編號：2091117