發(fā)布時(shí)間：2018-06-29 21:36

  本文選題：跳頻通信 + 軟件無線電　； 參考：《哈爾濱工業(yè)大學(xué)》2014年碩士論文

【摘要】：跳頻技術(shù)是軍事通信領(lǐng)域重要的通信技術(shù)之一，也是在民用通信領(lǐng)域有著廣泛應(yīng)用的先進(jìn)技術(shù)，其優(yōu)秀的抗干擾、抗截獲能力以及在通信組網(wǎng)方面的良好性能，使它在現(xiàn)代通信中占有重要的地位。本文通過研究跳頻通信的基本理論，以此為基礎(chǔ)利用軟件無線電技術(shù)完成了高速寬帶跳頻系統(tǒng)基帶處理單元的設(shè)計(jì)，并利用自主設(shè)計(jì)的Xilinx FPGA硬件平臺(tái)實(shí)現(xiàn)了從發(fā)信機(jī)到接收機(jī)的整套跳頻基帶處理功能。 在硬件方面，以設(shè)計(jì)并制作完成的基帶開發(fā)板為基礎(chǔ)，完成了所需核心芯片的配置、調(diào)試工作，為后續(xù)工作打下了良好的基礎(chǔ)。首先，DDS芯片與ADC芯片需要一個(gè)高度穩(wěn)定的系統(tǒng)時(shí)鐘，從硬件設(shè)計(jì)的角度選擇ADI公司的AD9516芯片，通過串行總線完成了時(shí)鐘芯片的配置工作，從而能夠?yàn)镈DS芯片和ADC芯片提供優(yōu)質(zhì)的時(shí)鐘輸入；其次，對(duì)高性能的DDS芯片AD9914完成了配置工作，分析了DDS芯片的性能；最后，完成了對(duì)高速ADC芯片和DAC芯片的配置工作，保證了后續(xù)數(shù)字信號(hào)處理工作和測(cè)試工作的順利進(jìn)行。 在軟件方面，通過ISE完成了收發(fā)信機(jī)基帶處理模塊的設(shè)計(jì)，包括DPSK調(diào)制與解調(diào)、DDS頻率控制和跳頻的同步捕獲與跟蹤。在跳頻同步的設(shè)計(jì)上，采取了通過能量檢測(cè)進(jìn)行滑動(dòng)調(diào)整的自同步法，介紹了同步的具體流程和實(shí)現(xiàn)方法，分析了系統(tǒng)同步捕獲的性能和跟蹤的精度。詳細(xì)說明了DPSK的解調(diào)方法，從信號(hào)處理、位同步提取、載波跟蹤幾個(gè)方面進(jìn)行了介紹。 最后，，將設(shè)計(jì)完成的基帶處理模塊與射頻模塊相連接搭建了高速寬帶的跳頻系統(tǒng)。系統(tǒng)頻率跳變速度20kHop/s，跳頻點(diǎn)數(shù)255個(gè)，系統(tǒng)帶寬500MHz。在收信機(jī)端，將解調(diào)數(shù)據(jù)通過FPGA測(cè)試管腳送至示波器觀察，驗(yàn)證了解調(diào)的正確性；同時(shí)利用ISE自帶的Chipscope軟件觀察基帶處理模塊中的關(guān)鍵信號(hào)，確保了各主要模塊的正常工作，驗(yàn)證了方案的可行性與系統(tǒng)的正確性。
[Abstract]:Frequency hopping (FH) is one of the most important communication technologies in the field of military communication. It is also an advanced technology widely used in the field of civil communication. It has excellent anti-jamming, anti-interception capability and good performance in communication networking. Make it play an important role in modern communication. Based on the basic theory of frequency hopping communication, the design of baseband processing unit of high speed broadband frequency hopping system is completed by using software radio technology. The FH baseband processing function from transmitter to receiver is realized by using Xilinx FPGA hardware platform. In the aspect of hardware, based on the design and manufacture of the baseband development board, the configuration and debugging of the core chip are completed, which lays a good foundation for the follow-up work. First of all, the DDS chip and ADC chip need a highly stable system clock. The AD9516 chip of ADI Company is selected from the point of view of hardware design, and the configuration of the clock chip is completed by serial bus. It can provide high quality clock input for DDS chip and ADC chip. Secondly, the configuration of high performance DDS chip AD9914 is completed, and the performance of DDS chip is analyzed. Finally, the configuration of high speed ADC chip and DAC chip is completed. The following digital signal processing and testing work are ensured. In the aspect of software, the design of baseband processing module of transceiver is completed through ISE, including DPSK modulation and demodulation, DDS frequency control and synchronous acquisition and tracking of frequency hopping. In the design of frequency hopping synchronization, the self-synchronization method of sliding adjustment through energy detection is adopted, the concrete flow and realization method of synchronization are introduced, and the performance of system synchronization acquisition and the tracking accuracy are analyzed. The demodulation method of DPSK is described in detail, including signal processing, bit synchronization extraction and carrier tracking. Finally, the designed baseband processing module is connected with the RF module to build a high speed broadband frequency hopping system. The frequency hopping speed of the system is 20 kHops, the number of hopping points is 255, and the bandwidth of the system is 500 MHz. At the receiver end, the demodulation data is sent to the oscilloscope through the FPGA test pin to verify the correctness of the demodulation. At the same time, the key signals in the baseband processing module are observed by using the Chipscope software of ISE to ensure the normal operation of the main modules. The feasibility of the scheme and the correctness of the system are verified.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN914.41

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 姬宗嶺;數(shù)字通信技術(shù)的應(yīng)用與發(fā)展[J];兵團(tuán)教育學(xué)院學(xué)報(bào);1999年04期

2 王喜風(fēng);王可人;金虎;;基于Tent映射雙向耦合映象格子的寬間隔跳頻序列及其性能分析[J];電訊技術(shù);2011年05期

3 王清泉;短波跳頻電臺(tái)的發(fā)展趨勢(shì)[J];電訊技術(shù);1997年04期

4 劉亞擎;茹樂;杜興民;楊軍;;基于跳頻和調(diào)制跳變的無線通信抗截獲新技術(shù)研究與展望[J];電光與控制;2008年09期

5 李少謙;擴(kuò)、跳頻通信技術(shù)的發(fā)展和展望[J];電子科技大學(xué)學(xué)報(bào);1996年S3期

6 蔣定順,金力軍;高速跳頻通信系統(tǒng)同步技術(shù)研究[J];電子科技大學(xué)學(xué)報(bào);2005年01期

7 林臻;蔣啟凡;陳元曦;;跳頻技術(shù)的基本原理及其在GSM網(wǎng)絡(luò)中的應(yīng)用[J];電信技術(shù);2006年10期

8 周俊峰,陳濤;基于FPGA的直接數(shù)字頻率合成器的設(shè)計(jì)和實(shí)現(xiàn)[J];電子技術(shù)應(yīng)用;2002年12期

9 陳亞丁;劉曉暉;程郁凡;李少謙;;超高速跳頻通信系統(tǒng)的實(shí)現(xiàn)及抗干擾性能[J];電子與信息學(xué)報(bào);2007年09期

10 向浩;姚遠(yuǎn);宋偉霖;;跳頻電臺(tái)綜合測(cè)試技術(shù)[J];國(guó)外電子測(cè)量技術(shù);2010年10期

相關(guān)博士學(xué)位論文 前1條

1 陳利虎;跳頻信號(hào)的偵察技術(shù)研究[D];國(guó)防科學(xué)技術(shù)大學(xué);2009年

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