本文選題：無線多媒體傳感網(wǎng) + OFDM基帶�。� 參考：《東南大學(xué)》2014年博士論文

【摘要】：無線多媒體傳感器網(wǎng)絡(luò)(WMSN)是一種感知并傳遞圖像、音視頻多媒體信息的網(wǎng)絡(luò),可利用多載波傳輸?shù)恼活l分復(fù)用(OFDM)技術(shù)頻譜利用率高和抗多徑衰落能力強等優(yōu)點提高網(wǎng)絡(luò)數(shù)據(jù)傳輸可靠性,但目前OFDM基帶核心電路如信道估計與均衡、糾錯、傅里葉變換等部分,存在著實現(xiàn)上較復(fù)雜、成本高、芯片面積大、功耗高等問題。論文綜述了信道估計與均衡、糾錯等關(guān)鍵技術(shù)的國內(nèi)外研究現(xiàn)狀,改進(jìn)適用于無線多媒體傳感網(wǎng)的信道估計與均衡、糾錯算法,優(yōu)化了信道估計與均衡、系統(tǒng)級FFT以及級聯(lián)碼RTL級電路,較好地降低了OFDM整體電路的復(fù)雜度與電路功耗,完成了邏輯功能仿真、FPGA驗證、DC綜合、后端版圖設(shè)計及功耗分析。論文的主要工作與創(chuàng)新點：1)提出了一種適用于WMSN的高糾錯能力串行級聯(lián)碼糾錯算法,利用改進(jìn)的行列分離的軟入軟出(SISO)交織器構(gòu)造新的串行級聯(lián)編譯碼器,在高斯和廣義瑞利信道下能獲得優(yōu)良的糾錯性能；2)改進(jìn)了OFDM基帶系統(tǒng)的LMMSE信道估計算法和MMSE均衡算法,其中該估計算法主要是借助導(dǎo)頻值合理估算信噪比和自相關(guān)矩陣,該均衡算法通過精選插值算法由部分均衡系數(shù)可獲得均衡器所有抽頭系數(shù)。改進(jìn)后的信道估計與均衡算法復(fù)雜度得到降低,以適應(yīng)無線多媒體傳感網(wǎng)系統(tǒng)低功耗要求；3)在信道均衡與估計的電路設(shè)計中,構(gòu)建了改進(jìn)型部分并行架構(gòu)乘法器,通過對乘法運算進(jìn)行操作數(shù)多級移位和分級處理,使乘法器整體硬件消耗降低約40%；在FFT電路實現(xiàn)中,提出了一種基于分裂基FFT算法的改進(jìn)型基2/4蝶形單元處理方法,通過加法器復(fù)用、中間寄存器插入和流水線架構(gòu),使得加法器的數(shù)量縮減了30%,提高了基帶系統(tǒng)的處理速度；4)糾錯級聯(lián)碼電路設(shè)計上,采用全局復(fù)用方法對RS碼譯碼器中求逆單元進(jìn)行設(shè)計,并在RS碼、卷積碼構(gòu)造的級聯(lián)碼結(jié)構(gòu)映射方面采用多級流水線技術(shù)、時分復(fù)用方法等,減少了譯碼電路關(guān)鍵路徑延時、時鐘周期數(shù)等,有效降低了譯碼電路的功耗,使級聯(lián)碼整體的異或門數(shù)量減少了20.8%；優(yōu)化了RS譯碼時關(guān)鍵方程求解單元的電路,使其乘法器數(shù)量減少了23.5%；充分利用分時復(fù)用和優(yōu)化設(shè)計數(shù)據(jù)轉(zhuǎn)移控制電路,使得卷積碼譯碼器中的加比選單元和路徑度量存儲單元的數(shù)量減少一半,滿足了電路低功耗要求。論文基于臺積電公司TSMC 0.13μm 1.2V CMOS工藝設(shè)計了信道估計與均衡器、級聯(lián)糾錯譯碼器和FFT/IFFT模塊,其中信道估計與均衡、級聯(lián)糾錯編譯碼、FFT電路這三大模塊的電路面積分別為0.503mm2、0.435mm2、1.008mm2,它們對應(yīng)的功耗分別為2.46mW, 4.29mW、7.04mW,這三者的面積和功耗分別只占OFDM基帶接收電路整體的44.8%、54.66%,較好地達(dá)到了設(shè)計的預(yù)期效果。最終把所設(shè)計這三部分關(guān)鍵電路嵌入到一款低功耗高速無線多媒體傳感網(wǎng)OFDM基帶芯片中,經(jīng)芯片實驗測試,滿足誤碼率低于10-6@10dB信噪比時系統(tǒng)設(shè)計指標(biāo)要求。
[Abstract]:Wireless Multimedia Sensor Network (WMSN) is a network that perceives and transmits video, audio and multimedia information. The orthogonal Frequency Division Multiplexing (OFDM) technique of multicarrier transmission can be used to improve the reliability of network data transmission, such as high spectral efficiency and strong anti-multipath fading ability. But at present, OFDM baseband core circuits such as channel estimation and equalization, error correction, etc. There are many problems in Fourier transform, such as complex implementation, high cost, large chip area and high power consumption. This paper summarizes the research status of key technologies such as channel estimation and equalization, error correction and so on, and improves the channel estimation and equalization algorithm for wireless multimedia sensor networks, and optimizes channel estimation and equalization. System level FFT and concatenated code RTL level circuits can reduce the complexity and power consumption of OFDM circuits. The logic function simulation and FPGA verification of DC synthesis, back-end layout design and power analysis are completed. The main work and innovation of this paper are as follows: (1) A novel serial concatenated code correction algorithm with high error-correcting capability for WMSN is proposed. A new serial concatenated codec is constructed by using the improved SISO Interleaver. The LMMSE channel estimation algorithm and the MMSE equalization algorithm for OFDM baseband systems are improved, in which the SNR and autocorrelation matrix are estimated reasonably by means of pilot values. All tap coefficients of equalizer can be obtained from partial equalization coefficients by selecting interpolation algorithm. The complexity of the improved channel estimation and equalization algorithm is reduced to meet the requirement of low power consumption in wireless multimedia sensor network systems. In the circuit design of channel equalization and estimation, an improved partially parallel architecture multiplier is constructed. By multistage shift and hierarchical processing of multiplication operation, the overall hardware consumption of multiplier is reduced by 40%. In the implementation of FFT circuit, an improved 2 / 4 butterfly unit processing method based on split radix FFT algorithm is proposed. By multiplexing adders, inserting intermediate registers and pipelining architecture, the number of adders is reduced by 30%, and the processing speed of baseband system is improved. 4) the design of error-correcting concatenated code circuit. The inverse unit in RS decoder is designed by using global multiplexing method. In the aspect of structure mapping of concatenated codes constructed by RS code and convolutional code, multistage pipeline technique and time division multiplexing method are used to reduce the critical path delay of decoding circuit. The number of clock cycles can effectively reduce the power consumption of the decoding circuit and reduce the number of XOR gates in the whole concatenated code by 20.8.The circuit of the key equation solving unit in RS decoding is optimized, and the number of multiplicators is reduced by 23.5. By making full use of time-sharing multiplexing and optimizing the design of data transfer control circuits, the number of Gaby selecting units and path measurement memory cells in convolutional code decoder is reduced by half, which meets the low power requirement of the circuit. Based on TSMC 0.13 渭 m 1.2V CMOS process, channel estimation and equalizer, concatenated error correction decoder and FFT / Ifft module are designed in this paper. The circuit area of the three modules of concatenated error correction code and decode FFT circuit is 0.503mm 2n / 0.435mm / 2 and 1.008mm / 2 respectively, and their corresponding power consumption is 2.46mW and 4.29mW / 7.04mW respectively. The area and power consumption of the three modules are only 44.8854.66mW of the whole OFDM baseband receiving circuit. Finally, the three key circuits are embedded into an OFDM baseband chip with low power consumption and high speed wireless multimedia sensor network. The experiment results show that the BER is lower than 10-610dB SNR.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2014
【分類號】：TN919.8;TP212.9
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本文編號：2065914