本文選題：余數(shù)系統(tǒng) + 數(shù)字信號(hào)處理�。� 參考：《電子科技大學(xué)》2014年碩士論文

【摘要】：隨著現(xiàn)代通信系統(tǒng)、密碼系統(tǒng)、圖像處理系統(tǒng)、網(wǎng)絡(luò)處理器系統(tǒng)等復(fù)雜度日益增加,并行處理技術(shù)結(jié)合Very Large Scale Integration (VLSI)技術(shù)已成為各領(lǐng)域共同的發(fā)展方向�；赩LSI技術(shù)的專用Digital Signal Processing (DSP)芯片在完成復(fù)雜的信源編碼、信道譯碼、解調(diào)、信號(hào)變換等高速信號(hào)處理中具有不可替代的地位,而處理速度和功耗的矛盾是VLSI設(shè)計(jì)中面臨的重大問題,并行處理技術(shù)是有效的解決方式之一。而并行處理的研究方向中,余數(shù)系統(tǒng)Residue Number System (RNS)所代表的并行數(shù)值表征系統(tǒng)具有算法前端的適應(yīng)性,進(jìn)而成為并行處理技術(shù)的重要研究方向之一。應(yīng)用RNS后將大大改善傳統(tǒng)并行處理器中的單個(gè)處理單元的性能。與傳統(tǒng)二進(jìn)制數(shù)值表征系統(tǒng)相比,RNS在算法級(jí)的并行性同時(shí)也使得其基本運(yùn)算,如模加法／模乘法,大小比較、符號(hào)檢測(cè)、余數(shù)基構(gòu)建等成為了其實(shí)際應(yīng)用中的關(guān)鍵問題。余數(shù)系統(tǒng)余數(shù)基組間相互獨(dú)立的特性,使得余數(shù)系統(tǒng)在差錯(cuò)控制方面必然將各個(gè)領(lǐng)域產(chǎn)生較大影響,進(jìn)而推進(jìn)余數(shù)系統(tǒng)的在并行處理技術(shù)中的應(yīng)用。近年來出現(xiàn)的陣列軟件無線電技術(shù)在多模式通信及高速信號(hào)處理中具有重要作用,同時(shí)隨著集成電路制造工藝進(jìn)入深亞微米階段,芯片內(nèi)噪聲所帶來的片上誤碼己成為不可忽略的問題。在信息處理速度以及功耗等控制的研究方向之外,信息的可靠傳輸、存儲(chǔ)也是余數(shù)系統(tǒng)的重要研究方向之一。本文圍繞基于RRNS的檢錯(cuò)和糾錯(cuò)能力等問題,提出一種類比于信道編碼中線性系統(tǒng)分組碼的信道編碼、信道譯碼設(shè)計(jì)方法的糾錯(cuò)算法結(jié)構(gòu)。定義了通過基于中國(guó)剩余定理Chinese Reminder Theory (CRT)的基擴(kuò)展Base Extension (BEX)計(jì)算方法得到的擴(kuò)展余數(shù)xk+s,s=1,2,…,r完成信道編碼的功能,并通過定義特殊校驗(yàn)矩陣HRRNS以完成校正子向量的計(jì)算。并通過類比線性分組碼中標(biāo)準(zhǔn)陣以及校正子譯碼的概念,定義了基于RRNS碼的檢錯(cuò)/糾錯(cuò)結(jié)構(gòu)。在上述RRNS碼差錯(cuò)控制結(jié)構(gòu)下,本文對(duì)前述RRNS信道編碼設(shè)計(jì)進(jìn)行改進(jìn),進(jìn)而使得新提出的糾錯(cuò)算法具有良好的"time x area"性能。本文將對(duì)比國(guó)外主要的三類基于Redundant Residue Number System (RRNS)的單錯(cuò)誤糾錯(cuò)算法：1.基于Mixed Radix Conversion (MRC)的基擴(kuò)展計(jì)算方法以及校正子計(jì)算,通過一致性方程求解對(duì)單個(gè)錯(cuò)誤進(jìn)行定位及糾錯(cuò)；2.同本文提出算法中偽校正子計(jì)算部分相同,并利用偽校正子中“量值”與單個(gè)余數(shù)錯(cuò)誤的對(duì)應(yīng)關(guān)系完成對(duì)單個(gè)錯(cuò)誤的定位及糾錯(cuò)；3.運(yùn)用MRC方法結(jié)合數(shù)值縮放技術(shù)建立縮放值與錯(cuò)誤向量的映射,進(jìn)而完成單個(gè)錯(cuò)誤的定位及糾錯(cuò)。本文在提出糾錯(cuò)算法的基本理論基礎(chǔ)以及實(shí)現(xiàn)結(jié)構(gòu)的同時(shí)給出對(duì)應(yīng)的完整的驗(yàn)證(功能仿真、門級(jí)仿真、Field Programmable Gate array (FPGA)加速驗(yàn)證)以及Application Specific integrated Circuit (ASIC)設(shè)計(jì)流程。本文將從延時(shí)、資源消耗方面對(duì)比本文提出算法以及上述國(guó)外主要的三類算法,進(jìn)而說明本文提出的算法更加適用于VLSI的實(shí)現(xiàn),在本文的綜合結(jié)果對(duì)比分析中將對(duì)本文算法的自動(dòng)化設(shè)計(jì)、驗(yàn)證、綜合平臺(tái)進(jìn)行實(shí)現(xiàn),并采用該自動(dòng)化平臺(tái),對(duì)動(dòng)態(tài)范圍為64位、128位的模數(shù)組的RRNS進(jìn)行對(duì)比評(píng)估。
[Abstract]:With the modern communication system, the complexity of cryptographic system, image processing system and network processor system is increasing. Parallel processing technology combined with Very Large Scale Integration (VLSI) technology has become a common development direction. The special Digital Signal Processing (DSP) chip based on VLSI technology has completed the complex source coding. Code, channel decoding, demodulation, signal transformation and other high-speed signal processing have an irreplaceable position, and the contradiction between processing speed and power consumption is a major problem in VLSI design. Parallel processing technology is one of the effective solutions. In the research direction of parallel processing, the parallelism represented by the remainder system Residue Number System (RNS) The application of RNS will greatly improve the performance of the single processing unit in the traditional parallel processor. Compared with the traditional binary numerical representation system, the parallelism of RNS at the algorithm level also makes the basic operation, such as the addition of the model. The method / modulus multiplication, size comparison, symbol detection, and the remainder base construction have become the key problems in their practical applications. The independent characteristics of the remainder system remainder base groups make the remainder system have a great influence in the field of error control, and then promote the application of the remainder system in parallel processing technology in recent years. Array software radio plays an important role in multi mode communication and high speed signal processing. At the same time, with the integrated circuit manufacturing technology entering the deep sub micron stage, the on-chip bit error caused by the noise in the chip has become a problem that can not be ignored. The reliable transmission of interest and storage is one of the important research directions of the remainder system. In this paper, a kind of error correction algorithm structure for channel coding and channel decoding is proposed around the channel coding based on the error detection and error correction ability of RRNS, which is based on the Chinese remainder theorem Chinese Remind. Er Theory (CRT) based on extended Base Extension (BEX) algorithm obtains the extended residue xk+s, s=1,2,... R completes the function of channel coding and completes the calculation of the corrected subvectors by defining a special checksum matrix HRRNS. The error detection / error correction structure based on the RRNS code is defined by the concept of the standard array and the correction subcode in the analogical linear block code. Under the aforementioned RRNS code error control structure, the previous RRNS channel coding is designed in this paper. In this way, the proposed error correction algorithm has a good "time x area" performance. This paper compares the three major single error correction algorithms based on Redundant Residue Number System (RRNS) in foreign countries: 1. based on Mixed Radix Conversion (MRC) base extension calculation method and correction subcalculation, through the consistency equation solution Location and error correction for a single error; 2. the location and error correction of a single error are completed by the corresponding relationship between the pseudo corrector and the error of a single remainder in the pseudo corrector. 3. the mapping of the scaling value and the error vector by the MRC method combined with the numerical scaling technique is used. Complete the basic theoretical basis of the error correction algorithm and the implementation of the structure, this paper gives the corresponding complete verification (functional simulation, gate level simulation, Field Programmable Gate array (FPGA) acceleration verification) and Application Specific integrated Circuit (ASIC) design process. This article will be from extension In the aspect of resource consumption, the algorithm and the three main foreign algorithms are compared in this paper. Then the proposed algorithm is more suitable for the implementation of VLSI. In this paper, the automatic design, verification and comprehensive platform of this algorithm will be implemented in the comprehensive results contrast analysis, and the automatic platform is used for the dynamic range. The RRNS of the 64 bit, 128 bit module group is compared.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.22

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相關(guān)期刊論文 前1條

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本文編號(hào)：2055530