發(fā)布時(shí)間：2018-06-19 00:57

  本文選題：陣列雷達(dá)數(shù)字接收機(jī) + 通用串行接口總線　； 參考：《電子科技大學(xué)》2014年碩士論文

【摘要】：陣列雷達(dá)在國(guó)防中的應(yīng)用無(wú)處不在,它的發(fā)展對(duì)于一個(gè)國(guó)家的軍事實(shí)力有著深遠(yuǎn)的影響。而數(shù)字接收機(jī)作為陣列雷達(dá)中必不可少的一部分,它的性能往往決定了陣列雷達(dá)的性能。為了能用一個(gè)簡(jiǎn)單有效的方法實(shí)現(xiàn)對(duì)陣列雷達(dá)數(shù)字接收機(jī)的性能進(jìn)行評(píng)估,本文設(shè)計(jì)了一個(gè)對(duì)A/D變換器的相關(guān)指標(biāo)進(jìn)行測(cè)試的測(cè)試系統(tǒng),從而達(dá)到對(duì)陣列雷達(dá)數(shù)字接收機(jī)的相關(guān)性能進(jìn)行間接測(cè)試的目的。整個(gè)測(cè)試系統(tǒng)是由硬件和軟件兩部分構(gòu)成,硬件系統(tǒng)負(fù)責(zé)數(shù)據(jù)的采集、存儲(chǔ)以及傳輸;軟件系統(tǒng)負(fù)責(zé)各種功能的實(shí)現(xiàn),包括硬件檢測(cè)、硬件自檢、配置參數(shù)和數(shù)據(jù)傳輸。為了滿足測(cè)試系統(tǒng)的需求,一方面對(duì)硬件方案中的主要模塊進(jìn)行了論證,另一方面提出了軟件方案的整體架構(gòu),同時(shí)對(duì)硬件與軟件之間的交互作了簡(jiǎn)要的說(shuō)明。硬件系統(tǒng)需要將ADC過(guò)后的差分?jǐn)?shù)據(jù)通過(guò)SN65LVDS386芯片轉(zhuǎn)換成單端數(shù)據(jù)輸入到FPGA,然后采用兩片1M*16bit的SRAM完成對(duì)兩路ADC數(shù)據(jù)的緩存,最后將數(shù)據(jù)通過(guò)USB2.0接口上傳到計(jì)算機(jī)中。軟件系統(tǒng)分為FPGA邏輯設(shè)計(jì)和USB程序設(shè)計(jì)兩個(gè)部分。在設(shè)計(jì)完FPGA邏輯的主體框架后,對(duì)其中的主要功能模塊作了詳細(xì)說(shuō)明,涵蓋了采集模塊、SRAM存儲(chǔ)模塊、通道選擇模塊、USB傳輸模塊、自檢模塊和總體控制模塊等邏輯設(shè)計(jì)。USB程序設(shè)計(jì)部分又分為固件程序設(shè)計(jì)和功能程序設(shè)計(jì),本文除了闡述了固件程序的每個(gè)步驟,還對(duì)系統(tǒng)所需的功能函數(shù)的流程作了介紹。最后對(duì)系統(tǒng)的功能進(jìn)行了驗(yàn)證,并給出了相應(yīng)的驗(yàn)證結(jié)果,同時(shí)在與上級(jí)板卡聯(lián)調(diào)測(cè)試后給出了測(cè)試結(jié)果,驗(yàn)證結(jié)果顯示了系統(tǒng)功能的正確性,而測(cè)試結(jié)果表明測(cè)試系統(tǒng)符合預(yù)期期望,完成了對(duì)A/D指標(biāo)的測(cè)試。
[Abstract]:Array radar is widely used in national defense, and its development has a profound influence on the military strength of a country. As an indispensable part of array radar, the performance of digital receiver often determines the performance of array radar. In order to evaluate the performance of array radar digital receiver with a simple and effective method, this paper designs a testing system to test the relative indexes of the A / D converter. Thus, the correlation of array radar digital receiver can be indirectly tested. The whole test system is composed of hardware and software, the hardware system is responsible for data acquisition, storage and transmission, and the software system is responsible for the realization of various functions, including hardware detection, hardware self-testing, configuration parameters and data transmission. In order to meet the requirements of the test system, on the one hand, the main modules in the hardware scheme are demonstrated; on the other hand, the overall structure of the software scheme is proposed, and the interaction between hardware and software is briefly explained. The hardware system needs to convert the difference data after ADC into single terminal data input into FPGA through SN65LVDS386 chip, then use two pieces of 1MU 16bit SRAM to cache the two ADC data, and finally upload the data to the computer through USB2.0 interface. The software system is divided into two parts: FPGA logic design and USB program design. After designing the main frame of FPGA logic, the main function modules are described in detail, including the acquisition module, the SRAM storage module, the channel selection module and the USB transmission module. The logic design of self-checking module and total control module. USB program design is divided into firmware program design and function program design. This paper not only describes each step of firmware program, but also introduces the flow of the function required by the system. Finally, the function of the system is verified, and the corresponding verification results are given. At the same time, the test results are given after the test with the higher board card. The verification results show the correctness of the system function. The test results show that the test system meets the expected expectations and completes the test of the A / D index.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN957.5

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本文編號(hào)：2037598