本文選題：電荷泵鎖相環(huán) + 鑒頻鑒相器�。� 參考：《南京理工大學(xué)》2014年碩士論文

【摘要】：鎖相環(huán)(Phase-Locked Loop, PLL)是一種同步反饋系統(tǒng),它在很多領(lǐng)域都有著廣泛的應(yīng)用。電荷泵鎖相環(huán)(Charge Pump PLL,CPPLL)是目前鎖相環(huán)設(shè)計(jì)的主流,它具有鎖定相差小、高速等優(yōu)點(diǎn)。 首先,本文介紹了CPPLL的工作原理以及它的五個(gè)組成模塊——鑒頻鑒相器(PFD)、電荷泵(CP)、環(huán)路濾波器(LPF)、壓控振蕩器(VCO)和分頻器(Divider)的結(jié)構(gòu)和工作原理。 其次,將電荷泵鎖相環(huán)的五個(gè)模塊的不同結(jié)構(gòu)進(jìn)行了對(duì)比,確定這五個(gè)模塊在本設(shè)計(jì)中所采用的結(jié)構(gòu)。 接著,基于TSMC0.18um CMOS工藝,運(yùn)用ADS軟件設(shè)計(jì)了各模塊的具體電路。改進(jìn)的鑒頻鑒相器死區(qū)很小,約45ps。改進(jìn)的電荷泵的充、放電流失配很小,介于-0.71%和0.03%之間,電流變化率也很小,約1%。LC壓控振蕩器的中心頻率為2GHz,輸出頻率范圍為1.799GHz到2.567GHz。分頻器采用可以快速工作的TSPC-DFF結(jié)構(gòu)5級(jí)級(jí)聯(lián),實(shí)現(xiàn)了32分頻。系統(tǒng)整體仿真結(jié)果顯示輸出波形占空比接近50%,22us時(shí)鎖相環(huán)基本鎖定。 最后,采用Spectre工具,在tsmc18rf的模型庫(kù)下對(duì)鑒頻鑒相器和分頻器這兩個(gè)子模塊進(jìn)行了仿真,使用Virtuoso工具完成了這兩個(gè)子模塊的版圖設(shè)計(jì),并利用Calibre提取了它們版圖中的寄生參數(shù)并進(jìn)行了后仿真。最后,對(duì)鑒頻鑒相器和分頻器的前仿真結(jié)果和后仿真結(jié)果進(jìn)行了對(duì)比分析。
[Abstract]:Phase-Locked Loop (PLL) is a synchronous feedback system, which is widely used in many fields. Charge pump PLL (charge pump PLL) is the main design of PLL at present. It has the advantages of small locking phase difference and high speed. Firstly, this paper introduces the working principle of CPPLL and the structure and working principle of its five modules, the frequency discriminator PFDO, the charge pump, the loop filter, the VCO) and the divider Divider. Secondly, the different structures of the five modules of the charge pump PLL are compared, and the structure of the five modules in this design is determined. Then, based on TSMC 0.18um CMOS process, the specific circuits of each module are designed by using ads software. The improved phase discriminator has a very small dead zone of about 45 ps. The discharge loss distribution of the improved charge pump is very small, between -0.71% and 0.03%, and the current change rate is also very small. The central frequency of the voltage controlled oscillator is about 2 GHz, and the output frequency ranges from 1.799 GHz to 2.567 GHz. The frequency divider adopts TSPC-DFF structure 5 stage cascade which can work fast and realizes 32 frequency division. The simulation results show that the phase-locked loop is basically locked when the duty cycle of the output waveform is close to 50 and 22us. Finally, the two sub-modules of frequency discriminator and frequency divider are simulated by using Spectre tool under the tsmc18rf model library, and the layout design of the two sub-modules is completed by using the Virtuoso tool. The parasitic parameters in their layout are extracted by calibre and then simulated. Finally, the pre-simulation and post-simulation results of the phase discriminator and frequency divider are compared and analyzed.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TN911.8

【參考文獻(xiàn)】

相關(guān)期刊論文 前6條

1 楊青;李智群;;應(yīng)用于鎖相環(huán)的低電壓高性能電荷泵設(shè)計(jì)[J];電腦知識(shí)與技術(shù);2009年04期

2 王秀琴;江曉林;;高性能電荷泵的鎖相環(huán)電路[J];黑龍江科技學(xué)院學(xué)報(bào);2009年04期

3 魏建瑋;張迎雪;;鎖相環(huán)技術(shù)綜述[J];科技信息(學(xué)術(shù)研究);2008年36期

4 張?jiān)?衣曉峰;洪志良;;基于CMOS工藝的低相位噪聲LC壓控振蕩器[J];微電子學(xué);2006年02期

5 簡(jiǎn)元?jiǎng)P;解光軍;毛佳佳;;一種應(yīng)用于CMOS鎖相環(huán)的電荷泵設(shè)計(jì)[J];合肥工業(yè)大學(xué)學(xué)報(bào)(自然科學(xué)版);2012年11期

6 胡仕剛;熊元新;徐征;;一種2.5V 0.25μm高速CMOS鎖相環(huán)設(shè)計(jì)[J];武漢大學(xué)學(xué)報(bào)(工學(xué)版);2006年05期

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