發(fā)布時(shí)間：2018-06-05 02:29

  本文選題：并網(wǎng)逆變器 + 軟件鎖相環(huán)��； 參考：《南京理工大學(xué)》2014年碩士論文

【摘要】：能源危機(jī)導(dǎo)致當(dāng)今社會(huì)對太陽能等新能源的渴求越來越旺盛,而通過光伏技術(shù)產(chǎn)生的直流電必須要經(jīng)過逆變器變?yōu)榻涣麟娙缓蟛⑷氍F(xiàn)有電網(wǎng)才能得到最大程度的利用。因此能夠鎖定電網(wǎng)頻率及相位的鎖相環(huán)技術(shù)的好壞將直接影響到逆變器的性能。如何利用DSP等數(shù)字芯片,設(shè)計(jì)出一個(gè)可以克服各種電網(wǎng)畸變及故障的軟件鎖相環(huán),是當(dāng)今科學(xué)研究的熱點(diǎn)問題。 本文首先論述的鎖相環(huán)技術(shù)的發(fā)展歷史及前景,簡單闡述了傳統(tǒng)的鎖相環(huán)技術(shù),指出了它們的缺點(diǎn)并提出了現(xiàn)階段的電網(wǎng)條件下對鎖相環(huán)的要求。 論文的第二部分給出了鎖相環(huán)的結(jié)構(gòu)框圖,并將鎖相環(huán)分為三個(gè)部分：鑒相器、環(huán)路濾波器、壓控振蕩器,并給出了它們的數(shù)學(xué)模型；分析了鑒相器的基本原理并給出了它的鑒相特性,說明了常用的幾種環(huán)路濾波器。 在前面的基礎(chǔ)上,分析了單同步旋轉(zhuǎn)坐標(biāo)系鎖相環(huán)(SSRF-SPLL)的基本原理和結(jié)構(gòu),并利用MATLAB對其在各種電網(wǎng)畸變(如三相電壓不平衡、電壓突降、頻率突降等)下的表現(xiàn)進(jìn)行了仿真。仿真結(jié)果與數(shù)學(xué)分析相吻合,證明了三相不平衡時(shí)由于負(fù)序分量的影響,SSRF-SPLL的表現(xiàn)不佳。 分析了雙同步坐標(biāo)系解耦軟件鎖相環(huán)(DDSRF-SPLL)和基于二階廣義積分的軟件鎖相環(huán)(SOGI-SPLL)的設(shè)計(jì)思路及結(jié)構(gòu)框圖,利用數(shù)學(xué)模型分析和仿真研究了它們的性能。結(jié)果證明兩種鎖相環(huán)可以濾除負(fù)序分量,因此在三相不平衡及高次諧波存在時(shí)都有較好的表現(xiàn)。 最后,簡單介紹了所用的TMS320F28335芯片并以它為基礎(chǔ)搭建了實(shí)驗(yàn)平臺(tái),設(shè)計(jì)了軟件的工作流程并為三種鎖相環(huán)編寫的相應(yīng)的程序；設(shè)計(jì)了一個(gè)調(diào)理電路使得A/D采樣模塊可以采集三相電壓；最后的結(jié)果證明了前面的理論分析。
[Abstract]:Because of the energy crisis, the demand for new energy, such as solar energy, is more and more strong. The direct current generated by photovoltaic technology must be converted from inverter to AC and then integrated into the existing power grid to get the maximum utilization. Therefore, the performance of the inverter will be directly affected by the PLL technology which can lock the frequency and phase of the power grid. How to design a software phase-locked loop (PLL) which can overcome all kinds of power network aberrations and faults by using digital chips such as DSP is a hot issue in current scientific research. In this paper, the development history and prospect of phase-locked loop (PLL) technology are discussed, the traditional PLL technology is briefly described, their shortcomings are pointed out and the requirements of PLL in the current power grid are put forward. In the second part of the paper, the structure block diagram of PLL is given, and the PLL is divided into three parts: phase discriminator, loop filter, voltage-controlled oscillator, and their mathematical models are given. The basic principle of the phase detector is analyzed, and its phase discrimination characteristics are given, and several common loop filters are explained. On the basis of the above, the basic principle and structure of SSRF-SPLL in single synchronous rotating coordinate system are analyzed, and the performance of SSRF-SPLL under various power grid distortions (such as three-phase voltage imbalance, voltage sudden drop, frequency abrupt drop) is simulated by MATLAB. The simulation results agree with the mathematical analysis and prove that the performance of SSRF-SPLL is not good due to the negative sequence component in the three-phase unbalance. The design idea and structure block diagram of DDSRF-SPLL and SOGI-SPLL based on second order generalized integral are analyzed. The performance of DDSRF-SPLL is analyzed and simulated by mathematical model. The results show that the two PLLs can filter out the negative sequence components, so they have better performance in the presence of three-phase unbalance and high-order harmonics. Finally, the TMS320F28335 chip is introduced briefly and the experimental platform is built based on it. The working flow of the software is designed and the corresponding program for the three PLL is designed. A conditioning circuit is designed so that the A / D sampling module can collect the three-phase voltage.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TM464;TN911.8

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本文編號：1980040