本文選題：無線通信 + FPGA�。� 參考：《電子科技大學》2014年碩士論文

【摘要】：本文結(jié)合通信原理基礎知識介紹了無線收發(fā)信機中頻及基帶的各部分實現(xiàn)過程,所采用的方法具有典型性和實用性,而且不失創(chuàng)新性。本文采用一片Cyclone III系列的FPGA作為基帶算法核心處理器,系統(tǒng)整體采用QPSK調(diào)制解調(diào)方式,在發(fā)射機端實現(xiàn)了串并轉(zhuǎn)換、符號映射、基帶成形濾波等核心算法;在接收機端實現(xiàn)了載波同步、符號同步以及幀同步等核心算法。本文通過對比各個方案的特點,結(jié)合模塊化設計的特殊要求最后選擇典型的超外差結(jié)構(gòu)實現(xiàn)收發(fā)信機的硬件電路設計。本文選擇ADI公司的正交變頻器實現(xiàn)基帶信號的調(diào)制與解調(diào),并選擇通信系統(tǒng)專用的TxDAC和RxADC實現(xiàn)了基帶信號的數(shù)/模與模/數(shù)變換。此外本文介紹了本振時鐘源(小數(shù)分頻PLL)的驅(qū)動程序設計,使得中頻及射頻的本振頻率可細調(diào),調(diào)整步進為50KHz。發(fā)射機對輸入串行數(shù)據(jù)首先進行加擾,然后按照QPSK調(diào)制方式進行了星座映射。發(fā)射機的脈沖成形濾波器為跟升余弦滾降濾波器,在本文中采用了基于FPGA的FIR濾波器的實現(xiàn)結(jié)構(gòu)。接收機的重點是同步。本文通過對標準科斯塔斯環(huán)進行研究并結(jié)合硬件電路的實際情況最后采用了反饋補償法載波同步。此外,本文在符號同步算法的實現(xiàn)上有所創(chuàng)新,提出了一種基于反饋環(huán)路形式的積分反饋式早遲門法。載波同步與符號同步在實現(xiàn)結(jié)構(gòu)上相似,都采用反饋環(huán)路的形式。試驗證明本文采用的載波同步與符號同步算法原理可行、性能良好。本文中的FPGA開發(fā)采用“自頂向下”的設計思路,將復雜的功能模塊劃分成功能單一的底層模塊,再由Verilog HDL語言逐一描述。FPGA具有極強的實時性和并行處理能力,可以滿足通信系統(tǒng)對處理器性能的需求。本文的最終成果實現(xiàn)了中頻段140MHz的通信,同時,通過配合射頻前端模塊實現(xiàn)了2.45GHz射頻段的無線通信。本文的基帶部分具有1M symbol/s的符號率,并具備2M bps的數(shù)據(jù)傳輸速率。為了方便測試,本文設計了完善的對外交換數(shù)據(jù)的通信接口,該通信接口具備數(shù)據(jù)緩存功能,為將上層主機(PC、MCU)數(shù)據(jù)源注入收發(fā)機系統(tǒng)提供了途徑,同時也增強了系統(tǒng)的實用性。
[Abstract]:In this paper, the realization process of if and baseband of wireless transceiver is introduced based on the basic knowledge of communication principle. The method adopted is typical, practical and innovative. In this paper, a Cyclone III series of FPGA is used as the core processor of baseband algorithm, and the whole system adopts QPSK modulation and demodulation mode. The core algorithms such as serial-parallel conversion, symbol mapping, baseband shaping filtering and so on are implemented in the transmitter. The core algorithms such as carrier synchronization, symbol synchronization and frame synchronization are implemented at the receiver end. By comparing the characteristics of each scheme and combining the special requirements of modular design, this paper chooses the typical superheterodyne structure to realize the hardware circuit design of transceiver. In this paper, the quadrature frequency converter of ADI Company is selected to realize the modulation and demodulation of baseband signal, and the TxDAC and RxADC, which are special for communication system, are selected to realize the digital / analog and A / D conversion of baseband signal. In addition, this paper introduces the driver design of the local oscillator clock source (fractional divider PLL), which makes the local frequency of if and RF can be fine-tuned and the step is adjusted to 50 KHz. The transmitter scrambled the input serial data and then mapped the constellation according to QPSK modulation. The pulse shaping filter of the transmitter is the following cosine roll down filter. The FIR filter based on FPGA is adopted in this paper. The focus of the receiver is synchronization. In this paper, the standard Kostas loop is studied and the feedback compensation method is used to synchronize the carriers. In addition, in this paper, the implementation of symbol synchronization algorithm is innovated, and an integral feedback early and late gate method based on feedback loop is proposed. Carrier synchronization and symbol synchronization are similar in structure, and both adopt feedback loop. The experimental results show that the carrier synchronization and symbol synchronization algorithms are feasible and have good performance. The development of FPGA in this paper adopts the idea of "top-down" design. The complex function module is divided into a single bottom module, and then described by Verilog HDL language one by one, it has strong real-time and parallel processing ability. It can meet the requirement of processor performance in communication system. The final achievement of this paper is to realize the communication of 140MHz in the middle frequency band, and to realize the wireless communication of the radio frequency segment of 2.45GHz by cooperating with the RF front-end module. The baseband of this paper has a symbol rate of 1m symbol/s and a data transmission rate of 2m bps. In order to facilitate the test, this paper designs a perfect communication interface for data exchange. The communication interface has the function of data cache, which provides a way to inject the data source of PC / MCU into the transceiver system, and at the same time enhances the practicability of the system.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN791;TN859

【參考文獻】

相關(guān)博士學位論文 前1條

1 林華杰;軟件無線電理論及應用技術(shù)研究[D];西北工業(yè)大學;2004年

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本文編號：1964876