本文選題：數(shù)字中頻接收機(jī) + 射頻前端模塊��； 參考：《河北工業(yè)大學(xué)》2015年碩士論文

【摘要】：本論文課題來(lái)源于中國(guó)電子科技集團(tuán)公司第十三研究所“無(wú)線(xiàn)語(yǔ)音偵聽(tīng)系統(tǒng)”,該項(xiàng)目需要對(duì)載波頻率為450MHz至460MHz、數(shù)據(jù)速率為200KBps、調(diào)制方式為二進(jìn)制相移鍵控(BPSK)或差分二進(jìn)制相移鍵控(DBPSK)的語(yǔ)音PCM編碼信號(hào)進(jìn)行接收、解調(diào)、解碼和播放存儲(chǔ)。在此項(xiàng)目背景下,本文研究設(shè)計(jì)了一套靈敏度高、抗噪聲能力強(qiáng)、適用多種解調(diào)方式的無(wú)線(xiàn)接收機(jī)。本文從現(xiàn)有通信技術(shù)入手,以軟件定義無(wú)線(xiàn)電(SDR)的思想和結(jié)構(gòu)為基礎(chǔ),設(shè)計(jì)并實(shí)現(xiàn)了一套數(shù)字中頻無(wú)線(xiàn)接收機(jī),其中包括三部分:一是射頻前端模塊(RFAF),此模塊包括天線(xiàn)、低噪聲放大器(LNA)、帶通濾波器(BPF)、頻率源、下混頻器和中頻放大器等,其功能是處理射頻模擬信號(hào),對(duì)其進(jìn)行接收、放大、濾波、混頻,最終產(chǎn)生一個(gè)頻率和幅度固定的中頻信號(hào);二是數(shù)字中頻處理模塊,此模塊包括模數(shù)轉(zhuǎn)換器(ADC)、數(shù)模轉(zhuǎn)換器(DAC)和數(shù)字信號(hào)處理芯片(DSP或者FPGA),其功能是對(duì)中頻信號(hào)進(jìn)行采樣,并利用數(shù)字信號(hào)處理技術(shù)完成解調(diào)解碼等工作;三是接口和上位機(jī)處理模塊,此模塊提供了接收機(jī)與計(jì)算機(jī)的接口,在必要時(shí)進(jìn)行數(shù)據(jù)的存儲(chǔ)和分析處理,具體到本文,需要對(duì)解調(diào)解碼出來(lái)的語(yǔ)音信號(hào)進(jìn)行去噪聲處理。本文在設(shè)計(jì)過(guò)程中,使用simulink進(jìn)行了系統(tǒng)級(jí)仿真和可行性驗(yàn)證、使用ADS進(jìn)行了射頻模塊的仿真和優(yōu)化、使用Altium Designer進(jìn)行了PCB板設(shè)計(jì)并進(jìn)行了射頻部分的硬件實(shí)驗(yàn)、使用modelsim和matlab進(jìn)行了FPGA和解調(diào)解碼算法仿真優(yōu)化、最終使用SignalTap等工具進(jìn)行了中頻部分的硬件調(diào)試和實(shí)驗(yàn)。根據(jù)軟件仿真和硬件調(diào)試結(jié)果,本文設(shè)計(jì)的數(shù)字中頻無(wú)線(xiàn)接收機(jī)達(dá)到如下參數(shù)指標(biāo):射頻部分接收靈敏度到達(dá)-100dB,1KHz帶外相位噪聲小于-60dBc,頻道切換時(shí)間小于60us;數(shù)字中頻模塊輸入信號(hào)信噪比(SNR)最低可達(dá)5dB、FPGA最高運(yùn)行頻率可達(dá)200MHz;通過(guò)改進(jìn)的譜減法進(jìn)行語(yǔ)音去噪,在實(shí)際應(yīng)用中明顯降低了接收者的聽(tīng)覺(jué)疲勞,提高了語(yǔ)音信號(hào)可懂度。
[Abstract]:This thesis comes from the 13th Research Institute of China Electronic Science and Technology Corporation, "Wireless Voice listening system". This project needs to receive, demodulate, decode and store speech PCM code signals with carrier frequencies ranging from 450MHz to 460MHz, data rate 200KBps, modulation mode by binary phase-shift keying (BPSK) or differential binary phase-shift keying (DBPSK). Under the background of this project, a set of wireless receiver with high sensitivity, strong anti-noise ability and suitable for various demodulation methods is designed. Based on the idea and structure of software defined radio SDR (SDR), a set of digital if wireless receiver is designed and implemented in this paper, which includes three parts: one is RF front-end module (RFAFN), which includes antenna, and the other is radio frequency front-end module (RF front-end module). Low noise amplifier (LNA), bandpass filter (BPF), frequency source, lower mixer and if amplifier, etc. Its function is to process RF analog signal, receive, amplify, filter, mix frequency, and finally produce a fixed frequency and amplitude if signal; The second is digital intermediate frequency processing module, which includes A / D converter (A / D converter), D / A converter (DAC) and digital signal processing chip (DSP) or FPGA. Its function is to sample if signal and complete demodulation and decoding by means of digital signal processing technology. The third is the interface and the upper computer processing module which provides the interface between the receiver and the computer. The data is stored and analyzed when necessary. In this paper it is necessary to remove the noise from the demodulated and decoded speech signal. In the design process, the system level simulation and feasibility verification are carried out with simulink, the RF module is simulated and optimized with ADS, the PCB board is designed with Altium Designer and the hardware experiment of RF part is carried out. Modelsim and matlab are used to simulate and optimize the FPGA and demodulation decoding algorithm. Finally, the hardware debugging and experiment of if part are carried out by using SignalTap and other tools. According to the results of software simulation and hardware debugging, The digital if wireless receiver designed in this paper achieves the following parameters: the sensitivity of the RF part reaches -100dBU 1kHz out-of-band phase noise is less than -60dBc, the channel switching time is less than 60us.The SNR of the input signal of the digital intermediate frequency module is the lowest. The highest operating frequency of FPGA is up to 200MHz, and the speech noise is removed by improved spectral subtraction. In practical application, the hearing fatigue of the receiver is obviously reduced, and the intelligibility of speech signal is improved.
【學(xué)位授予單位】：河北工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN851

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本文編號(hào)：1963195